Hitachi H8/3008 Hardware Manual page 492

φ
A to A ,
23 0
CS
n
AS
RD
(read)
D to D
15 0
(read)
HWR, LWR
(write)
D to D
15 0
(write)
476
T
1
t
t
WSD
t
AS2
t
WDD
Figure 19.8 Basic Bus Cycle: Three-State Access
T
2
t
ACC4
t
ACC4
ACC2
t
WSW2
t
WDS2
T
3
t
RDS