Timer Interrupt Status Register A (Tisra) - Hitachi H8/3008 Hardware Manual

8.2.4

Timer Interrupt Status Register A (TISRA)

TISRA is an 8-bit readable/writable register that indicates GRA compare match or input capture
and enables or disables GRA compare match and input capture interrupt requests.
Bit
—
Initial value
Read/Write —
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRA is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Input Capture/Compare Match Interrupt Enable A2 (IMIEA2): Enables or disables
the interrupt requested by the IMFA2 when IMFA2 flag is set to 1.
Bit 6
IMIEA2 Description
0 IMIA2 interrupt requested by IMFA2 flag is disabled
1 IMIA2 interrupt requested by IMFA2 flag is enabled
7 6 5
IMIEA2 IMIEA1
1 0 0
R/W R/W
Input capture/compare match interrupt enable A2 to A0
These bits enable or disable interrupts by the IMFA flags
4 3
IMIEA0 — IMFA2
0 1
R/W — R/(W)*
Input capture/compare match
flags A2 to A0
Status flags indicating GRA
compare match or input capture
Reserved bit
2 1 0
IMFA1 IMFA0
0 0 0
R/(W)* R/(W)*
(Initial value)
183