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8-Bit, Two-State-Access Areas: Figure 6.10 shows the timing of bus control signals for an 8-bit,
two-state-access area. The upper data bus (D
pin is always high. Wait states cannot be inserted.
Read access
Write access
Note: n = 7 to 0
Figure 6.10 Bus Control Signal Timing for 8-Bit, Two-State-Access Area
15
φ
Address bus
CS
n
AS
RD
D
to D
15
8
D
to D
7
0
HWR
LWR
D
to D
15
8
D
to D
7
0
) is used in accesses to these areas. The LWR
to D
8
Bus cycle
T
T
1
External address in area n
Valid
Invalid
High
Valid
Undetermined data
2
123
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