Table of Contents
Advertisement
Bits 7 and 6—Reserved: These bits can be written and read, but they do not enable or disable
interrupts.
Bits 5 to 0—IRQ
to IRQ
5
IRQ
to IRQ
interrupts.
5
0
Bits 5 to 0
IRQ5E to IRQ0E Description
0
IRQ
1
IRQ
5.2.5
IRQ Sense Control Register (ISCR)
ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the
inputs at pins IRQ
5
Bit
Initial value
Read/Write
R/W
Reserved bits
ISCR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 and 6—Reserved: These bits can be written and read, but they do not select level or
falling-edge sensing.
Bits 5 to 0—IRQ
to IRQ
5
interrupts IRQ
to IRQ
5
sensing.
Bits 5 to 0
IRQ5SC to IRQ0SC Description
0
1
Enable (IRQ5E to IRQ0E): These bits enable or disable
0
to IRQ
interrupts are disabled
5
0
to IRQ
interrupts are enabled
5
0
to IRQ
.
0
7
6
—
—
IRQ5SC
0
0
R/W
Sense Control (IRQ5SC to IRQ0SC): These bits select whether
0
are requested by level sensing of pins IRQ
0
Interrupts are requested when IRQ
Interrupts are requested by falling-edge input at IRQ
5
4
IRQ4SC
IRQ3SC
0
0
R/W
R/W
IRQ to IRQ sense control
5
These bits select level sensing or falling-edge
sensing for IRQ to IRQ interrupts
to IRQ
5
3
2
IRQ2SC
IRQ1SC
0
0
R/W
R/W
0
5
0
to IRQ
, or by falling-edge
5
0
inputs are low
0
to IRQ
5
(Initial value)
1
0
IRQ0SC
0
0
R/W
R/W
(Initial value)
0
83
Advertisement
Table of Contents
