Timer Interrupt Status Register C (Tisrc) - Hitachi H8/3008 Hardware Manual

8.2.6

Timer Interrupt Status Register C (TISRC)

TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Bit
Initial value
Read/Write
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2 Description
0 OVI2 interrupt requested by OVF2 flag is disabled
1 OVI2 interrupt requested by OVF2 flag is enabled
Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by the
OVF1 when OVF1 flag is set to 1.
Bit 5
OVIE1 Description
0 OVI1 interrupt requested by OVF1 flag is disabled
1 OVI1 interrupt requested by OVF1 flag is enabled
7 6 5
— OVIE2 OVIE1
1 0 0
— R/W R/W
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
4 3
OVIE0 — OVF2
0 1
R/W — R/(W)*
Reserved bit
2 1 0
OVF1 OVF0
0 0 0
R/(W)* R/(W)*
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
(Initial value)
(Initial value)
189