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Port
Description
Port 8 • 5-bit I/O port
• P8
to P8
have
2
0
schmitt inputs
Port 9 • 6-bit I/O port
Port A • 8-bit I/O port
• Schmitt inputs
140
Pins
Mode 1
P8
/CS
DDR = 0: generic input
4
0
DDR = 1 (reset value): CS
IRQ
P8
/IRQ
/CS
/
3
3
1
ADTRG
converter, and generic input
DDR = 0 (after reset): generic input
DDR = 1: CS
IRQ
P8
/IRQ
/CS
2
2
2
P8
/IRQ
/CS
DDR = 0 (after reset): generic input
1
1
3
DDR = 1: CS
IRQ
P8
/IRQ
0
0
P9
/IRQ
/SCK
Input and output (SCK
5
5
1
serial communication interfaces 1 and 0 (SCI1/0), IRQ
P9
/IRQ
/SCK
4
4
0
IRQ
P9
/RxD
3
1
P9
/RxD
2
0
P9
/TxD
1
1
P9
/TxD
0
0
PA
/TP
/
Output (TP
7
7
TIOCB
/A
grammable timing pattern
2
20
controller (TPC), input or
output (TIOCB
timer and generic input/output
PA
/TP
/TIOCA
/
TPC output (TP
6
6
2
A
(TIOCA
21
PA
/TP
/TIOCB
/
5
5
1
A
22
PA
/TP
/TIOCA
/
4
4
1
A
23
PA
/TP
/TIOCB
/
TPC output (TP
3
3
0
TCLKD
(TIOCB
timer input (TCLKD, TCLKC, TCLKB, TCLKA), and generic
PA
/TP
/TIOCA
/
2
2
0
input/output
TCLKC
PA
/TP
/TCLKB
1
1
PA
/TP
/TCLKA
0
0
Expanded Modes
Mode 2
input, CS
output, external trigger input (ADTRG) to A/D
3
1
output
1
and IRQ
input, CS
and CS
2
1
2
and CS
output
2
3
input, and generic input/output
0
, SCK
1
input, and 6-bit generic input/output
4
) from pro-
7
) for 16-bit
2
to TP
), 16-bit timer input and output
6
4
, TIOCB
, TIOCA
2
1
1
to TP
), 16-bit timer input and output
3
0
, TIOCA
, TCLKD, TCLKC, TCLKB, TCLKA), 8-bit
0
0
Mode 3
output
0
output, and generic input
3
, RxD
, RxD
, TxD
0
1
0
1
Address output (A
), and generic input/output
Mode 4
, TxD
) for
0
and
5
)
20
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