Summary of Contents for NXP Semiconductors LPC1311
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UM10375 LPC1311/13/42/43 User manual Rev. 3 — 14 June 2011 User manual Document information Info Content Keywords ARM Cortex-M3, microcontroller, USB, LPC1311, LPC1313, LPC1342, LPC1343, LPC1311/01, LPC1313/01 Abstract LPC1311/13/42/43 user manual...
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20110614 LPC1311/13/42/43 user manual Modifications: • Parts LPC1311/01 and LPC1313/01 added. • Modifications to the user manual applicable to parts LPC1311/01 and LPC1313/01 only: – SSP1 added for part LPC1313FBD48/01 in Chapter 3 “LPC13xx System configuration” Chapter 14 “LPC13xx SSP0/1”.
This user manual describes parts LPC1311, LPC1313, LPC1342, LPC1343. Part-specific features and registers are listed at the beginning of each chapter. Remark: The LPC13xx series consists of the LPC1300 series (parts LPC1311/13/42/43) and the LPC1300L series (parts LPC1311/01 and LPC1313/01). The LPC1300L series features the following enhancements over the LPC1300 series: •...
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Processor wake-up from Deep-sleep mode via a dedicated start logic using up to 40 of the functional pins. • Brownout detect with four separate thresholds for interrupt and one threshold for forced reset (four thresholds for forced reset on the LPC1311/01 and LPC1313/01 parts). • Power-On Reset (POR).
UM10375 NXP Semiconductors Chapter 1: LPC13xx Introductory information • System PLL allows CPU operation up to the maximum CPU rate without the need for a high-frequency crystal. May be run from the system oscillator or the internal RC oscillator. •...
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UM10375 NXP Semiconductors Chapter 1: LPC13xx Introductory information Table 2. Ordering options for LPC13xx Type number Flash Total Power UART SSP ADC Pins Package SRAM profiles RS-485 Fast+ channels LPC1342FBD48 16 kB 4 kB Device LQFP48 LPC1343FHN33 32 kB 8 kB...
SYSTEM CONTROL 002aae722 (1) LPC1342/43 only. (2) LQFP48 package only. (3) On LPC1313FBD48/01 only. (4) Windowed WatchDog Timer (WWDT) on LPC1311/01 and LPC1313/01 only. Fig 1. LPC13xx block diagram UM10375 All information provided in this document is subject to legal disclaimers.
8 and 10 SSP1 The SSP1 block is available on the LPC1313FBD48/01 only. SSP1 related registers and register bits are reserved for the following parts: LPC1311/13/42/43 and LPC1311FHN33/01 and LPC1313FHN33/01. BOD control The number of programmable BOD levels for forced reset is different for the LPC1300 and the LPC1300L series.
3.9.4.2): • IRC must be enabled for parts LPC1311/13/42/43. • IRC status has no effect for parts LPC1311/01 and LPC1313/01. Enabling sequence for UART clock Requirements for enabling the UART peripheral clock: • The UART pins must be configured in the IOCON block before the UART clock can be enabled...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.3 Pin description Table 6 shows pins that are associated with system control block functions. Table 6. Pin summary Pin name Pin description direction CLKOUT Clockout pin PIO0_0 to PIO0_11 Wake-up pins port 0...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.4 Clocking and power control Figure 3 for an overview of the LPC13xx Clock Generation Unit (CGU). The LPC131x include three independent oscillators. These are the system oscillator, the Internal RC oscillator (IRC), and the Watchdog oscillator. Each oscillator can be used for more than one purpose as required in a particular application.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Table 8. System memory remap register (SYSMEMREMAP, address 0x4004 8000) bit description Symbol Value Description Reset value System memory remap Boot Loader Mode. Interrupt vectors are re-mapped to Boot ROM. User RAM Mode. Interrupt vectors are re-mapped to Static RAM.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Table 10. System PLL control register (SYSPLLCTRL, address 0x4004 8008) bit description Symbol Value Description Reset value MSEL Feedback divider value. The division value M is the 0x000 programmed MSEL value + 1.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Table 12. USB PLL control register (USBPLLCTRL, address 0x4004 8010) bit description Symbol Value Description Reset value Post divider ratio P. The division ratio is 2 P. PSEL 0x00 P = 1...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.7 System oscillator control register This register configures the frequency range for the system oscillator. Table 14. System oscillator control register (SYSOSCCTRL, address 0x4004 8020) bit description Symbol Value Description Reset value...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.10 System reset status register The SYSRSTSTAT register shows the source of the latest reset event. The bits are cleared by writing a one to any of the bits. The POR event clears all other bits in this register, but if another reset signal (e.g., EXTRST) remains asserted after the POR signal...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.14 USB PLL clock source update enable register This register updates the clock source of the USB PLL with the new input clock after the USBPLLCLKSEL register has been written to. In order for the update to take effect at the USB PLL input, first write a zero to the USBPLLUEN register and then write a one to USBPLLUEN.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Remark: When switching clock sources, both clocks must be running before the clock source is updated. Table 23. Main clock source update enable register (MAINCLKUEN, address 0x4004 8074) bit description Symbol Value...
Disabled Enabled UART Enables clock for UART. Note that for the LPC1311/13/42/43, the UART pins must be configured in the IOCON block before the UART clock can be enabled. For the LPC1311/01 and LPC1313/01 no special enabling sequence is required.
This register configures the UART peripheral clock UART_PCLK. The UART_PCLK can be shut down by setting the DIV bits to 0x0. Remark: Note that for the LPC1311/13/42/43, the UART pins must be configured in the IOCON block before the UART clock can be enabled. For the LPC1311/01 and LPC1313/01 no special enabling sequence is required.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.21 SSP1 clock divider register This register configures the SSP1 peripheral clock SSP1_PCLK. The SSP1_PCLK can be shut down by setting the DIV bits to 0x0. Table 28. SSP1 clock divider register (SSP1CLKDIV, address 0x4004 809C) bit description...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Remark: When switching clock sources, both clocks must be running before the clock source is updated. The default clock source for the USB controller is the USB PLL output. For switching the clock source to the main clock, ensure that the system PLL and the USB PLL are running to make both clock sources available for switching.
Remark: When switching clock sources, both clocks must be running before the clock source is updated. Once the WWDT (LPC1311/01 and LPC1313/01 only) is enabled, the watchdog clock source cannot be changed. If the watchdog timer is running in Deep-sleep...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.30 CLKOUT clock source select register This register configures the clkout_clk signal to be output on the CLKOUT pin. All three oscillators and the main clock can be selected for the clkout_clk clock.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.35 BOD control register The BOD control register selects four separate threshold values for sending a BOD interrupt to the NVIC. Only one level is allowed for forced reset. Table 42. BOD control register (BODCTRL, address 0x4004 8150) bit description...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.37 Start logic edge control register 0 The STARTAPRP0 register controls the start logic inputs of ports 0 (PIO0_0 to PIO0_11) and 1 (PIO1_0 to PIO1_11) and the lower 8 inputs of port 2 (PIO2_0 to PIO2_7). This...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.39 Start logic reset register 0 Writing a one to a bit in the STARTRSRP0CLR register resets the start logic state. The bit assignment is identical to Table 44. The start-up logic uses the input signals to generate a clock edge for registering a start signal.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Every bit in the STARTAPRP1 register controls one port input and is connected to one wake-up interrupt in the NVIC. Bit 0 in the STARTAPRP1 register corresponds to interrupt 32, bit 1 to interrupt 33, up to bit 7 corresponding to interrupt 39 (see Table 66).
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration • BOD: Leaving the BOD circuit enabled will protect the part from a low voltage event occurring while the part is in Deep-sleep mode. However, the BOD circuit causes an additional current drain in Deep-sleep mode.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Remark: Reserved bits in this register must always be written as indicated. This register must be initialized correctly before entering Deep-sleep mode. Table 55. Power-down configuration register (PDRUNCFG, address 0x4004 8238) bit...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.5.48 Device ID register This device ID register is a read-only register and contains the device ID for each LPC13xx part. This register is also read by the ISP/IAP commands (see Section 21.13.11 Section 21.13.11).
CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. Oneadditional threshold level can be selected to cause a forced reset of the chip on the LPC1311/13/42/43 parts. Four additional threshold levels for forced reset can be selected on the LPC1311/01 and LPC1313/01 parts.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.9.1 Active mode In Active mode, the ARM Cortex-M3 core and memories are clocked by the system clock, and peripherals are clocked by the system clock or a dedicated peripheral clock. The chip is in Active mode after reset and the default power configuration is determined by the reset values of the PDRUNCFG and SYSAHBCLKCTRL registers.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3. Use the ARM Cortex-M3 Wait-For-Interrupt (WFI) instruction. 3.9.2.3 Wake-up from Sleep mode Sleep mode is exited automatically when an interrupt enabled by the NVIC arrives at the processor or a reset occurs. After wake-up due to an interrupt, the microcontroller returns to its original power configuration defined by the contents of the PDRUNCFG and the SYSAHBCLKDIV registers.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3. Select the power configuration after wake-up in the PDAWAKECFG (Table register. 4. If an external pin is used for wake-up, enable and clear the wake-up pin in the start logic registers...
62). 3. Write one to the SLEEPDEEP bit in the ARM Cortex-M3 SCR register. 4. For the LPC1311/13/42/43, ensure that the IRC is powered by setting bits IRCOUT_PD and IRC_PD to zero in the PDRUNCFG register before entering Deep power-down mode. This step is not required for the LPC1311/01 and LPC1313/01.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.10.2 Start logic The Deep-sleep mode is exited when the start logic indicates an interrupt to the ARM core. The various port pins (see Table 6) are connected to the start logic and serve as wake-up pins.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration irc_osc_clk sys_osc_clk PSEL<1:0> SYSPLLCLKSEL or USBPLLCLKSEL LOCK LOCK FCLKOUT DETECT analog section MSEL<4:0> (1) Not on USB PLL. Fig 5. System and USB PLL block diagram The block diagram of this PLL is shown in Figure 5.
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration 3.11.2 Power-down control To reduce the power consumption when the PLL clock is not needed, a Power-down mode has been incorporated. This mode is enabled by setting the SYSPLL_PD (or USBPLL_PD) bits to one in the Power-down configuration register (Table 55).
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration Table 57. PLL frequency parameters Parameter System PLL USB PLL FCLKOUT Frequency of sys_pllclkout; Frequency of usb_pllclkout; < 100 MHz < 100 MHz System PLL post divider ratio; PSEL USB PLL post divider ratio; PSEL bits...
UM10375 NXP Semiconductors Chapter 3: LPC13xx System configuration the Power-down mode is terminated by SYSPLL_PD (or USBPLL_PD) bits to zero in the Power-down configuration register (Table 55), the PLL will resume its normal operation and will make the lock signal high once it has regained lock on the input clock.
UM10375 Chapter 4: LPC13xx Power Management Unit (PMU) Rev. 3 — 14 June 2011 User manual 4.1 Introduction The PMU controls the Deep power-down mode. Four general purpose register in the PMU can be used to retain data during Deep power-down mode. 4.2 Register description Table 60.
UM10375 NXP Semiconductors Chapter 4: LPC13xx Power Management Unit (PMU) Table 61. Power control register (PCON, address 0x4003 8000) bit description …continued Symbol Value Description Reset value DPDFLAG Deep power-down flag Read: Deep power-down mode not entered. Write: No effect.
UM10375 Chapter 5: LPC13xx Power profiles Rev. 3 — 14 June 2011 User manual 5.1 How to read this chapter The power profiles are available for parts LPC1311/01 and LPC1313/01 only (LPC1300L series). 5.2 Features • Includes ROM-based application services •...
SYSPLLCLKSEL Fig 7. LPC1311/01 and LPC1313/01 clock configuration for power API use 5.4 Definitions The following elements have to be defined in an application that uses the power profiles: typedef struct _PWRD { void (*set_pll)(unsigned int cmd[], unsigned int resp[]);...
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles The routine returns a result code that indicates if the system PLL was successfully set (PLL_CMD_SUCCESS) or not (in which case the result code identifies what went wrong). The current system frequency value is also returned. The application should use this information to adjust other clocks in the device (the SSP, UART, and WDT clocks, and/or clockout).
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles CPU_FREQ_LTE can be used if the requested frequency should not be exceeded (such as overall current consumption and/or power budget reasons). CPU_FREQ_GTE helps applications that need a minimum level of CPU processing capabilities.
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles command[3] = 0; (*rom)->pWRD->set_pll(command, result); The above code specifies a 12 MHz PLL input clock, a system clock of no more than 40 kHz and no time-out while waiting for the PLL to lock. Since the maximum divider value...
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles The above code specifies a 12 MHz PLL input clock, a system clock of approximately 16.5 MHz and no locking time-out. set_pll returns PLL_CMD_SUCCESS in result[0] and 16000 in result[1]. The new system clock is 16 MHz.
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles Table 65. set_power routine Routine set_power Input Param0: main clock (in MHz) Param1: mode (PWR_DEFAULT, PWR_CPU_PERFORMANCE, PWR_ EFFICIENCY, PWR_LOW_CURRENT) Param2: system clock (in MHz) Result Result0: PWR_CMD_SUCCESS | PWR_INVALID_FREQ | PWR_INVALID_MODE The following definitions are needed for set_power routine calls:...
UM10375 NXP Semiconductors Chapter 5: LPC13xx Power profiles 5.6.1.4 Code examples The following examples illustrate some of the set_power features discussed above. 5.6.1.4.1 Invalid frequency (device maximum clock rate exceeded) command[0] = 75; command[1] = PWR_CPU_PERFORMANCE; command[2] = 75; (*rom)->pWRD->set_power(command, result);...
LPC1311/13. Interrupt 57 is available for part LPC1313FBD48/01 only (48-pin package, LPC1300L series). This interrupt is reserved on parts LPC1311/13/42/43 and LPC1311FHN33/01 and LPC1313FHN33/01. The implementation of start logic wake-up interrupts depends on how many PIO port pins...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller Table 66. Connection of interrupt sources to the Vectored Interrupt Controller Exception Vector Function Flag(s) Number Offset 39 to 0 start logic wake-up Each interrupt is connected to a PIO input pin serving...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.5 Vector table remapping The Cortex-M3 incorporates a mechanism that allows remapping the interrupt vector table to alternate locations in the memory map. This is controlled via the Vector Table Offset Register (VTOR) contained in the Cortex-M3.
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6 Register description The following table summarizes the registers in the NVIC as implemented in the LPC13xx. The Cortex-M3 User Guide provides a functional description of the NVIC. Table 67. Register overview: NVIC (base address 0xE000 E000)
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.8 Interrupt Clear-Pending Register 1 register The ICPR1 register allows clearing the pending state of the second group of peripheral interrupts, or for reading the pending state of those interrupts. Setting the pending state of interrupts is done through the ISPR0 and ISPR1 registers (Section 6.6.5...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.9 Interrupt Active Bit Register 0 The IABR0 register is a read-only register that allows reading the active state of the first 32 peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled.
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.10 Interrupt Active Bit Register 1 The IABR1 register is a read-only register that allows reading the active state of the second group of peripheral interrupts. This allows determining which peripherals are asserting an interrupt to the NVIC, and may also be pending if there are enabled.
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.11 Interrupt Priority Register 0 The IPR0 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 78. Interrupt Priority Register 0 (IPR0 - address 0xE000 E400) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.13 Interrupt Priority Register 2 The IPR2 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 80. Interrupt Priority Register 2 (IPR2 - address 0xE000 E408) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.15 Interrupt Priority Register 4 The IPR4 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 82. Interrupt Priority Register 4 (IPR4 - address 0xE000 E410) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.17 Interrupt Priority Register 6 The IPR6 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 84. Interrupt Priority Register 60 (IPR6 - address 0xE000 E418) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.19 Interrupt Priority Register 8 The IPR8 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 86. Interrupt Priority Register 8 (IPR8 - address 0xE000 E420) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.21 Interrupt Priority Register 10 The IPR10 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 88. Interrupt Priority Register 10 (IPR10 - address 0xE000 E428) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.23 Interrupt Priority Register 12 The IPR12 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 90. Interrupt Priority Register 12 (IPR12 - address 0xE000 E430) bit description...
UM10375 NXP Semiconductors Chapter 6: LPC13xx Interrupt controller 6.6.25 Interrupt Priority Register 14 The IPR14 register controls the priority of four peripheral interrupts. Each interrupt can have one of 32 priorities, where 0 is the highest priority. Table 92. Interrupt Priority Register 14 (IPR14 - address 0xE000 E438) bit description...
IOCON registers and register bits which are not used in all parts or packages. For the LPC1311/01 and LPC1313/01, a pseudo open-drain mode can be selected in the IOCON registers for each digital pins except the I2C pins. The open-drain mode is not available in the LPC1311/13/42/43 parts.
The possible on-chip resistor configurations are pull-up enabled, pull-down enabled, or no pull-up/pull-down. The default value is pull-up enabled. The pins are pulled up to 2.6 V for LPC1311/13/42/43 parts and pulled up to 3.3 V for LPC1311/01 and LPC1313/01 parts = 3.3 V).
1 disables the high-drive transistor. This option has no effect on the primary I C pins. Remark: The open-drain mode is only available on parts LPC1311/01 and LPC1313/01. 7.3.6 I C mode If the I...
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration The pin functions selectable in each IOCON register are listed in order (function 0/function 1/function 2/...) in the description column in Table Remark: The IOCON registers are listed in order of their memory locations in...
PIO3_2 IOCON_PIO3_2 Table 134 PIO3_3 IOCON_PIO3_3 Table 138 PIO3_4 IOCON_PIO3_4 yes, on yes, on Table 110 LPC1311/13 and LPC1311/13 and LPC1311/13/01. LPC1311/13/01. PIO3_5 IOCON_PIO3_5 yes, on yes, on Table 113 LPC1311/13 LPC1311/13 On LPC134x, PIO3_4 and PIO3_5 are not available. The corresponding pins are used for the USB D+ and D...
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.3 IOCON_nRESET_PIO0_0 Table 99. IOCON_nRESET_PIO0_0 register (IOCON_nRESET_PIO0_0, address 0x4004 400C) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function RESET. Selects function PIO0_0.
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration Table 104. IOCON_PIO2_8 register (IOCON_PIO2_8, address 0x4004 4024) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO2_8. MODE Selects function mode (on-chip pull-up/pull-down resistor...
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.10 IOCON_PIO0_3 Table 106. IOCON_PIO0_3 register (IOCON_PIO0_3, address 0x4004 402C) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO0_3. Selects function USB_VBUS (function not available on all parts).
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.12 IOCON_PIO0_5 Table 108. IOCON_PIO0_5 register (IOCON_PIO0_5, address 0x4004 4034) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO0_5 (open-drain pin). Selects I2C function SDA (open-drain pin).
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.14 IOCON_PIO3_4 Table 110. IOCON_PIO3_4 register (IOCON_PIO3_4, address 0x4004 403C) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO3_4. MODE Selects function mode (on-chip pull-up/pull-down resistor...
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.16 IOCON_PIO2_5 Table 112. IOCON_PIO2_5 register (IOCON_PIO2_5, address 0x4004 4044) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO2_5. MODE Selects function mode (on-chip pull-up/pull-down resistor...
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.18 IOCON_PIO0_6 Table 114. IOCON_PIO0_6 register (IOCON_PIO0_6, address 0x4004 404C) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO0_6. Selects function USB_CONNECT (function not available on all parts).
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.25 IOCON_SWCLK_PIOO_10 Table 121. IOCON_SWCLK_PIO0_10 register (IOCON_SWCLK_PIO0_10, address 0x4004 4068) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function SWCLK. Selects function PIO0_10.
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.28 IOCON_R_PIO0_11 Table 124. IOCON_R_PIO0_11 register (IOCON_R_PIO0_11, address 0x4004 4074) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function R. This function is reserved. Select one of the alternate functions below.
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.32 IOCON_PIO3_0 Table 128. IOCON_PIO3_0 register (IOCON_PIO3_0, address 0x4004 4084) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO3_0. Selects function DTR (function not available on all parts).
UM10375 NXP Semiconductors Chapter 7: LPC13xx I/O configuration 7.4.38 IOCON_PIO3_2 Table 134. IOCON_PIO3_2 register (IOCON_PIO3_2, address 0x4004 409C) bit description Symbol Value Description Reset value FUNC Selects pin function. All other values are reserved. Selects function PIO3_2. Selects function DCD (function not available on all parts, must also be configured in the corresponding IOCON_DCD_LOC register).
Reserved. 31:2 Reserved 7.4.44 IOCON_DSR_LOC Remark: For the LPC1311/01 and LPC1313/01 parts, the modem functions on pins PIO3_1 to PIO3_3 must be configured in the corresponding IOCONFIG registers and also in the IOCON_DSR_LOC, IOCON_DCD_LOC, and IOCON_RI_LOC registers (see Table 140 Table 101).
Reserved. 31:2 Reserved. 7.4.46 IOCON_RI_LOC Remark: For the LPC1311/01 and LPC1313/01 parts, the modem functions on pins PIO3_1 to PIO3_3 must be configured in the corresponding IOCONFIG registers and also in the IOCON_DSR_LOC, IOCON_DCD_LOC, and IOCON_RI_LOC registers (see Table 140 Table 101).
33 V PIO0_9/MOSI0/CT16B0_MAT1/SWO PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 002aae517 Transparent top view Fig 13. LPC1311/13 HVQFN33 package 8.4 Pin description Table 144 Table 145, the pins are listed in order of their port number. Supply pins and special function pins appear at the end.
UM10375 NXP Semiconductors Chapter 8: LPC13xx Pin configuration Table 144. LPC1313/42/43 LQFP48 pin description table …continued Symbol Start Type Reset Description logic state input PIO0_9/MOSI0/ I; PU PIO0_9 — General purpose digital input/output pin. CT16B0_MAT1/ MOSI0 — Master Out Slave In for SSP0.
= 3.3 V, pin is pulled up to 2.6 V for parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled; F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
= 3.3 V, pin is pulled up to 2.6 V for parts LPC1311/13/42/43 and pulled up to 3.3 V for parts LPC1311/01 and LPC1313/01); IA = inactive, no pull-up/down enabled. F = floating; floating pins, if not used, should be tied to ground or power to minimize power consumption.
Package GPIO port 0 GPIO port 1 GPIO port 2 GPIO port 3 Total GPIO pins LPC1311, HVQFN33 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 PIO3_2; PIO3_4; LPC1311/01 PIO3_5 LPC1313, LQFP48 PIO0_0 to PIO0_11 PIO1_0 to PIO1_11 PIO2_0 to PIO2_11 PIO3_0 to PIO3_5...
UM10375 NXP Semiconductors Chapter 9: LPC13xx General Purpose I/O (GPIO) 9.4 Register description Each GPIO register can be up to 12 bits wide and can be read or written using word or half-word operations at word addresses. Table 148. Register overview: GPIO (base address port 0: 0x5000 0000; port 1: 0x5001 0000, port 2: 0x5002 0000;...
UM10375 NXP Semiconductors Chapter 9: LPC13xx General Purpose I/O (GPIO) • If a pin is configured as GPIO output, the current value of GPIODATA register is driven to the pin. This value can be a result of writing to the GPIODATA register, or it can reflect the previous state of the pin if the pin is switched to GPIO output from GPIO input or another digital function.
UM10375 NXP Semiconductors Chapter 9: LPC13xx General Purpose I/O (GPIO) 9.4.4 GPIO interrupt both edges sense register Table 152. GPIO interrupt both edges sense register (GPIO0IBE, address 0x5000 8008 to GPIO3IBE, address 0x5003 8008) bit description Symbol Description Reset Access...
UM10375 NXP Semiconductors Chapter 9: LPC13xx General Purpose I/O (GPIO) Table 155. GPIO raw interrupt status register (GPIO0RIS, address 0x5000 8014 to GPIO3RIS, address 0x5003 8014) bit description Symbol Description Reset Access value 11:0 RAWST Raw interrupt status (x = 0 to 11).
UM10375 NXP Semiconductors Chapter 9: LPC13xx General Purpose I/O (GPIO) 9.5 Functional description 9.5.1 Write/read data operations In order for software to be able to set GPIO bits without affecting any other pins in a single write operation, bits [13:2] of a 14-bit wide address bus are used to create a 12-bit wide mask for write and read operations on the 12 GPIO pins for each port.
UM10375 Chapter 10: LPC13xx USB device controller Rev. 3 — 14 June 2011 User manual 10.1 How to read this chapter The USB device controller is available on parts LPC1342 and LPC1343 only. 10.2 Basic configuration The USB device is configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 158. USB related acronyms, abbreviations, and definitions used in this chapter Acronym/abbreviation Description Full-speed Light Emitting Diode Low Speed Maximum Packet Size Negative Acknowledge Phase Locked Loop Random Access Memory...
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 10.6 General description The architecture of the USB device controller is shown below in Figure MASTER USB_CONNECT INTERFACE EP_RAM SERIAL USB_DP REGISTER ACCESS INTERFACE INTERFACE CONTROL ENGINE register USB_DM interface (APB slave)
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 10.6.5 Register interface The Register Interface allows the CPU to control the operation of the USB Device Controller. It also provides a way to write transmit data to the controller and read receive data from the controller.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller For an OUT transaction, the USB ATX receives the bi-directional USB_DP and USB_DM signals of the USB bus. The Serial Interface Engine (SIE) receives the serial data from the ATX and converts it into a parallel data stream. The parallel data is written to the corresponding endpoint buffer.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 161. USB device controller clock sources Source Clock name Description ahb_sys_clk PCLK This is the system clock. Minimum frequency of this clock is 16 MHz. USB_MainClk USB_MainClk is the 48 MHz 500 ppm input clock. This...
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 163. USB Device Interrupt Status register (USBDevIntSt - address 0x4002 0000) bit description …continued Symbol Description Reset value USB core interrupt for physical endpoint 3. 0 = no interrupt. 1 = interrupt pending.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 164. USB Device Interrupt Enable register (USBDevIntEn - address 0x4002 0004) bit description Symbol Description Reset value FRAME_EN Frame interrupt. For isochronous packet transfers. 0 = no interrupt generated. 1 = interrupt generated when the corresponding bit in USBDevIntSt is set.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 164. USB Device Interrupt Enable register (USBDevIntEn - address 0x4002 0004) bit description Symbol Description Reset value CD_FULL_EN Command data register (USBCmdData) is full (Data can be read now). 0 = no interrupt generated.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 165. USB Device Interrupt Clear register (USBDevIntClr - address 0x4002 0008) bit description Symbol Description Reset value EP5_CLR USB core interrupt for physical endpoint 5. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is cleared.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 166. USB Device Interrupt Set register (USBDevIntSet - address 0x4002 000C) bit description Symbol Description Reset value FRAME_SET Frame interrupt. For isochronous packet transfers. 0 = no effect. 1 = the corresponding bit in USBDevIntSt is set.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 166. USB Device Interrupt Set register (USBDevIntSet - address 0x4002 000C) bit description Symbol Description Reset value RXENDPKT_SET The current packet in the endpoint buffer is transferred to the CPU.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 10.10.2.2 USB Command Data register (USBCmdData - 0x4002 0014) This register contains the data retrieved after executing a SIE command. When the data is ready to be read, the CD_FULL bit of the USBDevIntSt register is set. USBCmdData is a read only register.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 171. USB Receive Packet Length register (USBRxPLen - address 0x4002 0020) bit description Symbol Value Description Reset value PKT_LNGTH - The remaining number of bytes to be read from the currently selected endpoint’s buffer.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 173. USB Control register (USBCtrl - address 0x4002 0028) bit description Symbol Value Description Reset value RD_EN Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller For example, follow these steps: 1. USBCtrl = 0x01 2. delay(0) -- generate 1 clock cycle delay 3. pkt_length = USBTxPLen or USBRxPlen 10.10.4 Miscellaneous registers 10.10.4.1 USB Device FIQ Select register (USBDevFIQSel - 0x4002 002C) When a bit is set ‘1’, the corresponding interrupt will be routed to the high priority interrupt...
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 1. Command phase: the USBCmdCode register is written with the CMD_PHASE field set to the value 0x05 (Command), and the CMD_CODE field set to the desired command code. On completion of the command, the CCEMPTY bit of USBDevIntSt is set.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 175. SIE command code table Command name Recipient Code (Hex) Data phase Set Device Status Device Write 1 byte Get Device Status Device Read 1 byte Get Error Code Device...
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 177. Configure Device command description Symbol Description Reset value CONF_DEVICE Device is configured. All enabled non-control endpoints will respond. This bit is cleared by hardware when a bus reset occurs. When set, the UP_LED signal is driven LOW if the device is not in the suspended state (SUS=0).
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 180. Read interrupt Status byte 2 command description Bit Symbol Value Description Reset value 1:0 - reserved D_ST Device Status change interrupt 7:3 - reserved The device status change is cleared by issuing the Get device status command. All other endpoint interrupts are cleared by issuing select endpoint/clear interrupt command.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 181. Set Device Status command description Bit Symbol Value Description Reset value Suspend: The Suspend bit represents the current suspend state. When the device is suspended (SUS = 1) and the CPU writes a 0 into it, the device will generate a remote wake-up.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 10.11.9 Get Error Code (Command: 0xFF, Data: read 1 byte) Different error conditions can arise inside the SIE. The Get Error Code command returns the last error code that occurred. The 4 least significant bits form the error code.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller Table 183. Select Endpoint command description Bit Symbol Value Description Reset value Stalled endpoint indicator. The selected endpoint is not stalled. The selected endpoint is stalled. SETUP bit: the value of this bit is updated after each successfully received packet (i.e.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 10.11.12 Set Endpoint Status (Command: 0x40 - 0x49, Data: write 1 byte (optional)) The Set Endpoint Status command sets status bits 7:5 and 0 of the endpoint. The Command Code of Set Endpoint Status is equal to the sum of 0x40 and the physical endpoint number in hex.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller the SETUP data. If it is set then it should discard the previously read data, clear the PO bit by issuing a Select Endpoint/Clear Interrupt command, read the new SETUP data and again check the status of the PO bit.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 4. Select the system clock source by setting 0x01 (use system oscillator) in SYSPLLCLKSEL register (see Table 18). 5. Update the clock source by setting 1 in SYSPLLUEN register (see Table 19) register, and wait until clock source is updated.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller For non-isochronous endpoints when a full data packet is received without any errors, the endpoint generates a request for data transfer from its FIFO by generating an interrupt to the system.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller For OUT isochronous endpoints, the data will always be written irrespective of the buffer status. For IN isochronous endpoints, the data available in the buffer will be sent only if the buffer is validated;...
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 1. The host sends a data packet to the endpoint. The device hardware puts the packet into B_1, and generates an endpoint interrupt. 2. Software clears the endpoint interrupt and begins reading the packet data from B_1.
UM10375 NXP Semiconductors Chapter 10: LPC13xx USB device controller 6. Software clears the endpoint interrupt. Software fills B_1 with the third packet and validates it using the SIE Validate Buffer command. The active buffer is switched to B_2. 7. The device successfully sends the second packet from B_2 and generates an endpoint interrupt.
UM10375 Chapter 11: LPC13xx USB on-chip drivers Rev. 3 — 14 June 2011 User manual 11.1 How to read this chapter The USB device controller is available on parts LPC1342 and LPC1343 only. 11.2 Introduction The boot ROM contains a USB driver to simplify the USB application development. The USB driver implements the Human Interface Device (HID) and the Mass Storage Device (MSC) device class.
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers 11.3.2 USB initialization This function must be called by the application software after the clock and pin initialization. A pointer to the structure describing the USB device type is passed as a parameter to this function.
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers USB Driver 0x1FFF 1FF8 init_clk_pins Ptr to ROM Driver table init connect ROM Driver Table Device 2 Ptr to USB Driver Table 1 Ptr to Function 1 Ptr to Device Table 2...
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers DeviceInfo.DevDetailPtr = (uint32_t)&HidDevInfo; (*rom)->pUSBD->init(&DeviceInfo); 6. Add the USB interrupt handler to your project: USB_IRQHandler(void) (*rom)->pUSBD->isr(); 7. Call USB connect: USB Connect (*rom)->pUSBD->connect(TRUE); 11.5 USB driver structure definitions 11.5.1 ROM driver table...
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers Table 186. USB device information class structure Member Description DevType USB device class type USB_DEVICE_CLASS_HUMAN_INTERFACE(0x03) USB_DEVICE_CLASS_STORAGE(0x08) DevDetailPtr Pointer to the device information structure 11.5.4 Mass storage device information The following structure is used to pass the MSC device information:...
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers Table 187. Mass storage device information class structure Member Description MemorySize Memory size in number of bytes MSC_Write Write call back function. This function is provided by the application software. This function gets called when host sends a write command.
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers Table 188. Human interface device information class structure Member Description SampleInterval Interrupt endpoint (IN and OUT) sample interval in ms. InReport InReport call back function. This function is provided by the application software.
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers 11.6.2 Mass storage configuration, interface, and endpoint descriptors The USB driver reports the following descriptors during the enumeration process for a MSC device: Table 190. Mass storage descriptors Field Value Description...
UM10375 NXP Semiconductors Chapter 11: LPC13xx USB on-chip drivers Table 191. HID descriptors Field Value Description HID configuration descriptor bLength 0x09 Descriptor size in bytes bDescriptorType 0x02 The constant Configuration (0x02) wTotalLength 0x0029 Size of all data returned for this configuration in bytes...
LQFP48 packages only. 12.2 Basic configuration The UART is configured using the following registers: 1. Pins: For the LPC1311/13/42/43 parts, the UART pins must be configured in the IOCONFIG register block (Section 7.4) before the UART clocks can be enabled. For the LPC1311/01 and LPC1313/01 parts, no special enabling sequence is required.
Table 27). This clock is used by the UART baud rate generator. Remark: For LPC1311/13/42/43 parts, the UART pins must be configured in the corresponding IOCON registers before the UART clocks are enabled. For the LPC1311/01 and LPC1313/01 parts, no special enabling sequence is required.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 193. Register overview: UART (base address: 0x4000 8000) Name Access Address Description Reset offset value U0RBR 0x000 Receiver Buffer Register. Contains the next received character to be read. When DLAB=0. U0THR 0x000 Transmit Holding Register.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 12.6.1 UART Receiver Buffer Register (U0RBR - 0x4000 8000, when DLAB = 0, Read Only) The U0RBR is the top byte of the UART RX FIFO. The top byte of the RX FIFO contains the oldest character received and can be read via the bus interface.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 196. UART Divisor Latch LSB Register (U0DLL - address 0x4000 8000 when DLAB = 1) bit description Symbol Description Reset value DLLSB The UART Divisor Latch LSB Register, along with the U0DLM 0x01 register, determines the baud rate of the UART.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART If the IntStatus bit is one and no interrupt is pending and the IntId bits will be zero. If the IntStatus is 0, a non auto-baud interrupt is pending in which case the IntId bits identify the...
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 200. UART Interrupt Handling U0IIR[3:0] Priority Interrupt Interrupt source Interrupt value type reset 0100 Second RX Data Rx data available or trigger level reached in FIFO U0RBR Available (U0FCR0=1) Read UART FIFO...
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 201. UART FIFO Control Register (U0FCR - address 0x4000 8008, Write Only) bit description Symbol Value Description Reset value FIFOEN FIFO Enable UART FIFOs are disabled. Must not be used in the application.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 202. UART Line Control Register (U0LCR - address 0x4000 800C) bit description Symbol Value Description Reset Value Parity Enable Disable parity generation and checking. Enable parity generation and checking. Parity Select Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 203. UART0 Modem Control Register (U0MCR - address 0x4000 8010) bit description Symbol Value Description Reset value Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Example: Suppose the UART operating in type ‘550 mode has the trigger level in U0FCR set to 0x2, then, if Auto-RTS is enabled, the UART will de-assert the RTS output as soon as the receive FIFO contains 8 bytes (Table 201 on page 188).
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART UART TX start bits0..7 stop start bits0..7 stop start bits0..7 stop CTS pin Fig 21. Auto-CTS Functional Timing While starting transmission of the initial character, the CTS signal is asserted. Transmission will stall as soon as the pending transmission has completed. The UART will continue transmitting a 1 bit as long as CTS is de-asserted (high).
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 205. UART Line Status Register (U0LSR - address 0x4000 8014, Read Only) bit description …continued Bit Symbol Value Description Reset Value Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 12.6.10 UART Modem Status Register The U0MSR is a read-only register that provides status information on the modem input signals. U0MSR[3:0] is cleared on U0MSR read. Note that modem signals have no direct effect on the UART operation.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 12.6.12 UART Auto-baud Control Register (U0ACR - 0x4000 8020) The UART Auto-baud Control Register (U0ACR) controls the process of measuring the incoming clock/data rate for the baud rate generation and can be read and written at user’s discretion.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Two auto-baud measuring modes are available which can be selected by the U0ACR Mode bit. In Mode 0 the baud rate is measured on two subsequent falling edges of the UART Rx pin (the falling edge of the start bit and the falling edge of the least significant bit).
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 4. During the receipt of the start bit (and the character LSB for Mode = 0), the rate counter will continue incrementing with the pre-scaled UART input clock (UART_PCLK). 5. If Mode = 0, the rate counter will stop on next falling edge of the UART Rx pin. If Mode = 1, the rate counter will stop on the next rising edge of the UART Rx pin.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 12.6.15 UART Fractional Divider Register (U0FDR - 0x4000 8028) The UART Fractional Divider Register (U0FDR) controls the clock pre-scaler for the baud rate generation and can be read and written at the user’s discretion. This pre-scaler takes the APB clock and generates an output clock according to the specified fractional requirements.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART 12.6.15.1 Baud rate calculation UART can operate with or without using the Fractional Divider. In real-life applications it is likely that the desired baud rate can be achieved using several different Fractional Divider settings.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Calculating UART baudrate (BR) PCLK, = PCLK/(16 x BR) is an True integer? DIVADDVAL = 0 False MULVAL = 1 = 1.5 Pick another FR from = Int(PCLK/(16 x BR x FR the range [1.1, 1.9]...
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Although Table 211 describes how to use TxEn bit in order to achieve hardware flow control, it is strongly suggested to let UART hardware implemented auto flow control features take care of this, and limit the scope of TxEn to software flow control.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART Table 212. UART RS485 Control register (U0RS485CTRL - address 0x4000 804C) bit description …continued Symbol Value Description Reset value DCTRL Direction control enable Disable Auto Direction Control. Enable Auto Direction Control. OINV This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART The UART master transmitter will identify an address character by setting the parity (9th) bit to ‘1’. For data characters, the parity bit is set to ‘0’. Each UART slave receiver can be assigned a unique address. The slave can be programmed to either manually or automatically reject data following an address which is not theirs.
UM10375 NXP Semiconductors Chapter 12: LPC13xx UART When Auto Direction Control is enabled, the selected pin will be asserted (driven LOW) when the CPU writes data into the TXFIFO. The pin will be de-asserted (driven HIGH) once the last bit of data has been transmitted. See bits 4 and 5 in the RS485CTRL register.
UM10375 Chapter 13: LPC13xx I2C-bus controller Rev. 3 — 14 June 2011 User manual 13.1 How to read this chapter The I C-bus block is identical for all LPC13xx parts. 13.2 Basic configuration The I C-bus interface is configured using the following registers: 1.
C Fast-mode Plus Fast-Mode Plus supports a 1 Mbit/sec transfer rate to communicate with the I C-bus products which NXP Semiconductors is now providing. In order to use Fast-Mode Plus, the I C pins must be properly configured in the...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.6 Pin description Table 215. I C-bus pin description Type Description Input/Output C-bus Serial Data Input/Output C-bus Serial Clock The I C-bus pins must be configured through the IOCON_PIO0_4 (Table 107) and...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller I2EN I C Interface Enable. When I2EN is 1, the I C interface is enabled. I2EN can be cleared by writing 1 to the I2ENC bit in the I2CONCLR register. When I2EN is 0, the I interface is disabled.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 2. The General Call address has been received while the General Call bit (GC) in I2ADR is set. 3. A data byte has been received while the I C is in the master receiver mode.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Any of these registers which contain the bit 00x will be disabled and will not match any address on the bus. The slave address register will be cleared to this disabled state on reset.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 223. I2SCLL + I2SCLH values for selected I C clock values C mode C bit PCLK_I2C (MHz) frequency I2SCLH + I2SCLL Standard mode 100 kHz Fast-mode 400 kHz Fast-mode Plus 1 MHz I2SCLL and I2SCLH values should not necessarily be the same.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 225. I C Monitor mode control register (I2C0MMCTRL - 0x4000 001C) bit description Symbol Value Description Reset value MM_ENA Monitor mode enable. Monitor mode disabled. The I C module will enter monitor mode. In this mode the SDA output will be forced high.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Subsequent to an address-match detection, interrupts will be generated after each data byte is received for a slave-write transfer, or after each byte that the module “thinks” it has transmitted for a slave-read transfer. In this second case, the data register will actually contain data transmitted by some other slave on the bus which was actually addressed by the master.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Although the DATA_BUFFER register is primarily intended for use in monitor mode with the ENA_SCL bit = ‘0’, it will be available for reading at any time under any mode of operation.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller slave mode. The STA, STO and SI bits must be 0. The SI Bit is cleared by writing 1 to the SIC bit in the I2CONCLR register. THe STA bit should be cleared after writing the slave address.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller When the slave address and data direction bit have been transmitted and an acknowledge bit has been received, the SI bit is set, and the Status Register will show the status code. For master mode, the possible status codes are 0x40, 0x48, or 0x38. For slave mode, the possible status codes are 0x68, 0x78, or 0xB0.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller mode. After the address and direction bit have been received, the SI bit is set and a valid status code can be read from the Status register (I2STAT). Refer to Table 237 for the status codes and actions.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.10.2 Address Registers, I2ADDR0 to I2ADDR3 These registers may be loaded with the 7-bit slave address (7 most significant bits) to which the I C block will respond when programmed as a slave transmitter or receiver. The LSB (GC) is used to enable General Call address (0x00) recognition.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller SDA line SCL line (1) Another device transmits serial data. (2) Another device overrules a logic (dotted line) transmitted this I C master by pulling the SDA line low. Arbitration is lost, and this I C enters Slave Receiver mode.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller via the I C Clock Control Registers. See the description of the I2CSCLL and I2CSCLH registers for details. The output clock pulses have a duty cycle as programmed unless the bus is synchronizing with other SCL clock sources as described above.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 231. Abbreviations used to describe an I C operation Abbreviation Explanation START Condition 7-bit slave address Read bit (HIGH level at SDA) Write bit (LOW level at SDA) Acknowledge bit (LOW level at SDA)
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller The master transmitter mode may now be entered by setting the STA bit. The I C logic will now test the I C-bus and generate a START condition as soon as the bus becomes free.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 233. Master Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller successful transmission DATA to a Slave Receiver next transfer started with a Repeated Start condition Acknowledge received after the Slave address to Master receive mode, Acknowledge entry received after a = MR...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.11.2 Master Receiver mode In the master receiver mode, a number of data bytes are received from a slave transmitter (see Figure 35). The transfer is initialized as in the master transmitter mode. When the START condition has been transmitted, the interrupt service routine must load I2DAT with the 7-bit slave address and the data direction bit (SLA+R).
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 234. Master Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller successful transmission to DATA DATA a Slave transmitter next transfer started with a Repeated Start condition Not Acknowledge received after the Slave address to Master transmit mode, entry = MT arbitration lost in...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.11.3 Slave Receiver mode In the slave receiver mode, a number of data bytes are received from a master transmitter (see Figure 36). To initiate the slave receiver mode, I2ADR and I2CON must be loaded as follows: Table 235.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 237. Slave Receiver mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 237. Slave Receiver mode …continued Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller reception of the own Slave address and one DATA DATA P OR S or more Data bytes all are acknowledged last data byte received is Not P OR S acknowledged arbitration lost as...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.11.4 Slave Transmitter mode In the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see Figure 37). Data transfer is initialized as in the slave receiver mode. When I2ADR...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller Table 238. Slave Transmitter mode Status Status of the I C-bus Application software response Next action taken by I C hardware Code and hardware To/From I2DAT To I2CON (I2CSTAT) STA STO SI...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller reception of the own Slave address and one or more Data DATA DATA P OR S bytes all are acknowledged arbitration lost as Master and addressed as Slave last data byte transmitted. Switched...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller causes the I C block to enter the “not addressed” slave mode (a defined state) and to clear the STO flag (no other bits in I2CON are affected). The SDA and SCL lines are released (a STOP condition is not transmitted).
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller OTHER MASTER DATA CONTINUES other Master sends retry repeated START earlier Fig 38. Simultaneous Repeated START conditions from two masters 13.11.6.2 Data transfer after loss of arbitration Arbitration may be lost in the master transmitter and master receiver modes (see Figure 32).
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.11.6.4 I C-bus obstructed by a LOW level on SCL or SDA An I C-bus hang-up can occur if either the SDA or SCL line is held LOW by any device on the bus.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.11.8 Initialization In the initialization example, the I C block is enabled for both master and slave modes. For each mode, a buffer is used for transmission and reception. The initialization routine performs the following functions: •...
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 2. Set up the Slave Address to which data will be transmitted, and add the Write bit. 3. Write 0x20 to I2CONSET to set the STA bit. 4. Set up data to be transmitted in Master Transmit buffer.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 5. Set up Master Receive mode data buffer. 6. Initialize Master data counter. 7. Exit 13.12.5.4 State: 0x10 A Repeated START condition has been transmitted. The Slave Address + R/W bit will be transmitted, an ACK bit will be received.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 6. Write 0x04 to I2CONSET to set the AA bit. 7. Write 0x08 to I2CONCLR to clear the SI flag. 8. Increment Master Transmit buffer pointer 9. Exit 13.12.6.4 State: 0x30 Data has been transmitted, NOT ACK received. A STOP condition will be transmitted.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 4. Exit 5. Write 0x04 to I2CONSET to set the AA bit. 6. Write 0x08 to I2CONCLR to clear the SI flag. 7. Increment Master Receive buffer pointer 8. Exit 13.12.7.4 State: 0x58 Data has been received, NOT ACK has been returned.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 4. Initialize Slave data counter. 5. Exit 13.12.8.4 State: 0x78 Arbitration has been lost in Slave Address + R/W bit as bus Master. General call has been received and ACK has been returned. Data will be received and ACK returned. STA is set to restart Master mode after the bus is free again.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 13.12.8.8 State: 0x98 Previously addressed with General Call. Data has been received, NOT ACK has been returned. Received data will not be saved. Not addressed Slave mode is entered. 1. Write 0x04 to I2CONSET to set the AA bit.
UM10375 NXP Semiconductors Chapter 13: LPC13xx I2C-bus controller 2. Write 0x04 to I2CONSET to set the AA bit. 3. Write 0x08 to I2CONCLR to clear the SI flag. 4. Increment Slave Transmit buffer pointer. 5. Exit 13.12.9.4 State: 0xC0 Data has been transmitted, NOT ACK has been received. Not addressed Slave mode is entered.
UM10375 Chapter 14: LPC13xx SSP0/1 Rev. 3 — 14 June 2011 User manual 14.1 How to read this chapter The SSP0 block is identical for all LPC13xx parts. The SSP1 block is available on part LPC1313FBD48/01 only. 14.2 Basic configuration The SSP is configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 14.5 Pin description Table 240. SSP pin descriptions Interface pin name/function Type Pin description name Microwire SCK0/1 Serial Clock. SCK/CLK/SK is a clock signal used to synchronize the transfer of data. It is driven by the master and received by the slave.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 14.6 Clocking and power control The clocks and power to the SSP0 and SSP1 blocks are controlled by the following registers: 1. The SSP0/1 block can be enabled or disabled through the SYSAHBCLKCTRL...
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 Table 244: SSP Control Register 1 (SSP0CR1 - address 0x4004 0004, SSP1CR1 - address 0x4005 8004) bit description Symbol Value Description Reset value Loop Back Mode. During normal operation. Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 14.7.4 SSP Status Register This read-only register reflects the current status of the SSP controller. Table 246: SSP Status Register (SSP0SR - address 0x4004 000C, SSP1SR - address 0x4005 800C) bit description Symbol...
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 Table 248: SSP Interrupt Mask Set/Clear register (SSP0IMSC - address 0x4004 0014, SSP1IMSC - address 0x4005 8014) bit description Symbol Description Reset value RORIM Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 Table 250: SSP Masked Interrupt Status register (SSP0MIS - address 0x4004 001C, SSP1MIS - address 0x4005 801C) bit description Symbol Description Reset value RORMIS This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 DX/DR 4 to 16 bits a. Single frame transfer DX/DR 4 to 16 bits 4 to 16 bits b. Continuous/back-to-back frames transfer Fig 41. Texas Instruments Synchronous Serial Frame Format: a) Single and b) Continuous/back-to-back Two...
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 The CPHA control bit selects the clock edge that captures data and allows it to change state. It has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 In the case of a single word transmission, after all bits of the data word have been transferred, the SSEL line is returned to its idle HIGH state one SCK period after the last bit has been captured.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 SSEL MOSI MISO 4 to 16 bits a. Single transfer with CPOL=1 and CPHA=0 SSEL MOSI MISO 4 to 16 bits 4 to 16 bits b. Continuous transfer with CPOL=1 and CPHA=0 Fig 44. SPI frame format with CPOL = 1 and CPHA = 0 (a) Single and b) Continuous Transfer) In this configuration, during idle periods: •...
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 14.8.2.5 SPI format with CPOL = 1,CPHA = 1 The transfer signal sequence for SPI format with CPOL = 1, CPHA = 1 is shown in Figure 45, which covers both single and continuous transfers.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 8-bit control 4 to 16 bits of output data Fig 46. Microwire frame format (single transfer) 8-bit control 4 to 16 bits 4 to 16 bits of output data of output data Fig 47. Microwire frame format (continuous transfers) Microwire format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique.
UM10375 NXP Semiconductors Chapter 14: LPC13xx SSP0/1 latches each bit on the rising edge of SK. At the end of the frame, for single transfers, the CS signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter, that causes the data to be transferred to the receive FIFO.
UM10375 Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Rev. 3 — 14 June 2011 User manual 15.1 How to read this chapter The 16-bit timer blocks are identical for all LPC13xx parts. 15.2 Basic configuration The CT16B0/1 are configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) 15.5 Description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 253. Register overview: 16-bit counter/timer 0 CT16B0 (base address 0x4000 C000) Name Access Address Description Reset offset value TMR16B0IR 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 254. Register overview: 16-bit counter/timer 1 CT16B1 (base address 0x4001 0000) Name Access Address Description Reset offset value TMR16B1IR 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 255. Interrupt Register (TMR16B0IR - address 0x4000 C000 and TMR16B1IR - address 0x4001 0000) bit description Symbol Description Reset value MR0INT Interrupt flag for match channel 0. MR1INT Interrupt flag for match channel 1.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 260. Match Control Register (TMR16B0MCR - address 0x4000 C014 and TMR16B1MCR - address 0x4001 0014) bit description …continued Symbol Value Description Reset value MR1R Reset on MR1: the TC will be reset if MR1 matches it.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 261: Match registers (TMR16B0MR0 to 3, addresses 0x4000 C018 to 24 and TMR16B1MR0 to 3, addresses 0x4001 0018 to 24) bit description Symbol Description Reset value 15:0 MATCH Timer counter match value.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) 15.8.10 External Match Register (TMR16B0EMR and TMR16B1EMR) The External Match Register provides both control and status of the external match channels and external match pins CT16B0_MAT[2:0] and CT16B1_MAT[1:0]. If the match outputs are configured as PWM output in the PWMCON registers (Section 15.8.12), the function of the external match registers is determined by the PWM...
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 264. External Match Register (TMR16B0EMR - address 0x4000 C03C and TMR16B1EMR - address 0x4001 003C) bit description Symbol Value Description Reset value EMC2 External Match Control 2. Determines the functionality of External Match 2.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 266. Count Control Register (TMR16B0CTCR - address 0x4000 C070 and TMR16B1CTCR - address 0x4001 0070) bit description Symbol Value Description Reset value Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear...
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) Table 267. PWM Control Register (TMR16B0PWMC - address 0x4000 C074 and TMR16B1PWMC- address 0x4001 0074) bit description Symbol Value Description Reset value PWMEN1 PWM channel1 enable CT16Bn_MAT1 is controlled by EM1.
UM10375 NXP Semiconductors Chapter 15: LPC13xx 16-bit timer/counters (CT16B0/1) 15.10 Architecture The block diagram for counter/timer0 and counter/timer1 is shown in Figure MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER...
UM10375 Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Rev. 3 — 14 June 2011 User manual 16.1 How to read this chapter The 32-bit timer blocks are identical for all LPC13xx parts. 16.2 Basic configuration The CT32B0/1 are configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) 16.5 Description Each Counter/timer is designed to count cycles of the peripheral clock (PCLK) or an externally supplied clock and can optionally generate interrupts or perform other actions at specified timer values based on four match registers. Each counter/timer also includes one capture input to trap the timer value when an input signal transitions, optionally generating an interrupt.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 269. Register overview: 32-bit counter/timer 0 CT32B0 (base address 0x4001 4000) Name Access Address Description Reset offset value TMR32B0IR 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 270. Register overview: 32-bit counter/timer 1 CT32B1 (base address 0x4001 8000) Name Access Address Description Reset offset value TMR32B1IR 0x000 Interrupt Register (IR). The IR can be written to clear interrupts. The IR can be read to identify which of five possible interrupt sources are pending.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 271: Interrupt Register (TMR32B0IR - address 0x4001 4000 and TMR32B1IR - address 0x4001 8000) bit description Symbol Description Reset value MR0INT Interrupt flag for match channel 0. MR1INT Interrupt flag for match channel 1.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 276: Match Control Register (TMR32B0MCR - address 0x4001 4014 and TMR32B1MCR - address 0x4001 8014) bit description Symbol Value Description Reset value MR1S Stop on MR1: the TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) 16.8.8 Capture Control Register (TMR32B0CCR and TMR32B1CCR) The Capture Control Register is used to control whether the Capture Register is loaded with the value in the Timer Counter when the capture event occurs, and whether an interrupt is generated by the capture event.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 280: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C) bit description Symbol Value Description Reset value External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 280: External Match Register (TMR32B0EMR - address 0x4001 403C and TMR32B1EMR - address0x4001 803C) bit description Symbol Value Description Reset value 11:10 EMC3 External Match Control 3. Determines the functionality of External Match 3.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 282: Count Control Register (TMR32B0CTCR - address 0x4001 4070 and TMR32B1TCR - address 0x4001 8070) bit description Symbol Value Description Reset value Counter/Timer Mode. This field selects which rising PCLK edges can increment Timer’s Prescale Counter (PC), or clear...
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) Table 283: PWM Control Register (TMR32B0PWMC - 0x4001 4074 and TMR32B1PWMC - 0x4001 8074) bit description Symbol Value Description Reset value PWMEN1 PWM channel 1 enable CT32Bn_MAT1 is controlled by EM1.
UM10375 NXP Semiconductors Chapter 16: LPC13xx 32-bit timer/counters (CT32B0/1) 16.10 Architecture The block diagram for 32-bit counter/timer0 and 32-bit counter/timer1 is shown in Figure MATCH REGISTER 0 MATCH REGISTER 1 MATCH REGISTER 2 MATCH REGISTER 3 MATCH CONTROL REGISTER EXTERNAL MATCH REGISTER...
UM10375 Chapter 17: LPC13xx System tick timer Rev. 3 — 14 June 2011 User manual 17.1 How to read this chapter The system tick timer (SysTick timer) is part of the ARM Cortex-M3 core and is identical for all LPC13xx parts. 17.2 Basic configuration The system tick timer is configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 17: LPC13xx System tick timer 17.5 Operation The System Tick Timer is a 24-bit timer that counts down to zero and generates an interrupt. The intent is to provide a fixed 10 millisecond time interval between interrupts.
UM10375 NXP Semiconductors Chapter 17: LPC13xx System tick timer 17.6.1 System Timer Control and status register (CTRL - 0xE000 E010) The CTRL register contains control information for the System Tick Timer, and provides a status flag. Table 285. System Timer Control and status register (CTRL - 0xE000 E010) bit description...
UM10375 NXP Semiconductors Chapter 17: LPC13xx System tick timer Table 287. System Timer Current value register (VAL - 0xE000 E018) bit description Symbol Description Reset value 23:0 CURRENT Reading this register returns the current value of the System Tick counter. Writing any value clears the System Tick counter and the COUNTFLAG bit in STCTRL.
UM10375 NXP Semiconductors Chapter 17: LPC13xx System tick timer 17.7 Example timer calculations To use the system tick timer, do the following: 1. Program the LOAD register with the reload value RELOAD to obtain the desired time interval. 2. Clear the VAL register by writing to it. This ensures that the timer will count from the LOAD value rather than an arbitrary value when the timer is enabled.
User manual 18.1 How to read this chapter This chapter describes the WDT block without the windowed watchdog features and applies to the LPC1300 parts LPC1311/13/42/43. 18.2 Basic configuration The WDT is configured using the following registers: 1. Pins: The WDT uses no external pins.
UM10375 NXP Semiconductors Chapter 18: LPC13xx WatchDog Timer (WDT) 18.5 Description The Watchdog consists of a divide by 4 fixed pre-scaler and a 24-bit counter. The clock is fed to the timer via a pre-scaler. The timer decrements when clocked. The minimum value from which the counter decrements is 0xFF.
UM10375 NXP Semiconductors Chapter 18: LPC13xx WatchDog Timer (WDT) Watchdog reset or interrupt will occur any time the watchdog is running and has an operating clock source. Any clock source works in Sleep mode, and if a watchdog interrupt occurs in Sleep mode, it will wake up the device.
UM10375 NXP Semiconductors Chapter 18: LPC13xx WatchDog Timer (WDT) 18.7.4 Watchdog Timer Value register (WDTV - 0x4000 400C) The WDTV register is used to read the current value of Watchdog timer. When reading the value of the 24-bit timer, the lock and synchronization procedure takes up to 6 WDCLK cycles plus 6 PCLK cycles, so the value of WDTV is older than the actual value of the timer when it's being read by the CPU.
Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT) Rev. 3 — 14 June 2011 User manual 19.1 How to read this chapter This chapter describes the Windowed WDT available on the LPC1300L parts LPC1311/01 and LPC1313/01. 19.2 Basic configuration The WDT is configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT) 19.4 Applications The purpose of the Watchdog Timer is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, a watchdog event will be generated if the user program fails to "feed"...
UM10375 NXP Semiconductors Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT) Table 296: Watchdog Mode register (WDMOD - 0x4000 4000) bit description Symbol Value Description Reset value WDPROTECT Watchdog update mode. This bit is Set Only. The watchdog reload value (WDTC) can be changed at any time.
UM10375 NXP Semiconductors Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT) Table 298: Watchdog Timer Constant register (WDTC - 0x4000 4004) bit description Symbol Description Reset value 23:0 Count Watchdog time-out interval. 0x00 00FF 31:24 Reserved. Read value is undefined, only zero should be written.
UM10375 NXP Semiconductors Chapter 19: LPC13xx Windowed WatchDog Timer (WWDT) Table 301: Watchdog Timer Warning Interrupt register (WDWARNINT - 0x4000 4014) bit description Symbol Description Reset value WARNINT Watchdog warning interrupt compare value. 31:10 Reserved. Read value is undefined, only zero should be written.
UM10375 Chapter 20: LPC13xx Analog-to-Digital Converter (ADC) Rev. 3 — 14 June 2011 User manual 20.1 How to read this chapter The ADC block is identical for all LPC13xx parts. 20.2 Basic configuration The ADC is configured using the following registers: 1.
UM10375 NXP Semiconductors Chapter 20: LPC13xx Analog-to-Digital Converter (ADC) 20.5 Clocking and power control The peripheral clock to the ADC (PCLK) is provided by the system clock (see Figure This clock can be disabled through bit 13 in the SYSAHBCLKCTRL register...
UM10375 NXP Semiconductors Chapter 20: LPC13xx Analog-to-Digital Converter (ADC) Table 305: A/D Control Register (AD0CR - address 0x4001 C000) bit description Symbol Value Description Reset Value Start conversion when the edge selected by bit 27 occurs on CT32B0_MAT0. Timer match function does not need to be selected on the device pin.
UM10375 NXP Semiconductors Chapter 20: LPC13xx Analog-to-Digital Converter (ADC) 20.6.3 A/D Interrupt Enable Register (AD0INTEN - 0x4001 C00C) This register allows control over which A/D channels generate an interrupt when a conversion is complete. For example, it may be desirable to use some A/D channels to monitor sensors by continuously performing conversions on them.
UM10375 NXP Semiconductors Chapter 20: LPC13xx Analog-to-Digital Converter (ADC) Table 309: A/D Status Register (AD0STAT - address 0x4001 C030) bit description Symbol Description Reset Value DONE These bits mirror the DONE status flags that appear in the result register for each A/D channel.
21.14.6) and is part of the chip marking for some LPC13xx parts (see Table 311). Table 311. Bootloader versions Part Bootloader Top-side marking Notes version read by ISP/IAP LPC1311 no marking LPC1313 no marking LPC1342 Section 21.2.1. LPC1343 Section 21.2.1.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.2.1 Bootloader code version 5.2 notes In bootloader version 5.2 (LPC134x parts), the mass storage device state machine uses an uninitialized variable. This has two consequences: 1. In the user code, the memory location must be initialized as follows to create a work-around for this issue: *((unit32_t *)(0x1000 0054)) = 0x0;...
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware Assuming that power supply pins are at their nominal levels when the rising edge on RESET pin is generated, it may take up to 3 ms before PIO0_1 is sampled and the decision whether to continue with user code or ISP handler/USB is made.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.7 Criterion for Valid User Code The reserved ARM Cortex-M3 exception vector location 7 (offset 0x0000 001C in the vector table) should contain the 2’s complement of the check-sum of table entries 0 through 6.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.8.3 ISP data format The data stream is in UU-encoded format. The UU-encode algorithm converts 3 bytes of binary data in to 4 bytes of printable ASCII character set. It is more efficient than Hex format which converts 1 byte of binary data in to 2 bytes of ASCII hex.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.9 USB communication protocol The LPC134x is enumerated as a Mass Storage Class (MSC) device to a PC or another embedded system. In order to connect via the USB interface, the LPC134x must use the external crystal at a frequency of 12 MHz.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.13 ISP commands The following commands are accepted by the ISP command handler. Detailed status codes are supported for each command. The command handler sends the return code INVALID_COMMAND when an undefined command is received. Commands and return codes are in ASCII format.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware Table 321. ISP Write to RAM command Command Input Start Address: RAM address where data bytes are to be written. This address should be a word boundary. Number of Bytes: Number of bytes to be written. Count should be a multiple of 4...
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware Table 324. ISP Copy command Command Input Flash Address(DST): Destination flash address where data bytes are to be written. The destination address should be a 256 byte boundary. RAM Address(SRC): Source RAM address from where data bytes are to be read.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.13.14 ReadUID Table 332. ReadUID command Command Input None Return Code CMD_SUCCESS followed by four 32-bit words of a unique serial number in ASCII format. The word sent at the lowest address is sent first.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.14 IAP commands For in application programming the IAP routine should be called with a word pointer in register r0 pointing to memory (RAM) containing command code and parameters. Result of the IAP command is returned in the result table pointed to by register r1.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware suggested scheme is used for the parameter passing/returning then it might create problems due to difference in the C compiler implementation from different vendors. The suggested parameter passing scheme reduces such risk.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware Table 347. Flash configuration register (FLASHCFG, address 0x4003 C010) bit description Symbol Value Description Reset value FLASHTIM Flash memory access time. FLASHTIM +1 is equal to the number of system clocks used for flash access.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware 21.16.3 Signature generation result registers The signature generation result registers return the flash signature produced by the embedded signature generator. The 128-bit signature is reflected by the four registers FMSW0, FMSW1, FMSW2 and FMSW3.
UM10375 NXP Semiconductors Chapter 21: LPC13xx Flash memory programming firmware If signature generation is triggered via JTAG, the duration is in JTAG tck cycles, and tcy is the time in ns for one JTAG clock. Polling the SIG_DONE bit in FMSTAT is not possible in this case.
UM10375 Chapter 22: LPC13xx Serial Wire Debug (SWD) Rev. 3 — 14 June 2011 User manual 22.1 How to read this chapter The debug functionality is identical for all LPC13xx parts. 22.2 Features • Supports ARM Serial Wire Debug mode. •...
UM10375 NXP Semiconductors Chapter 22: LPC13xx Serial Wire Debug (SWD) Table 356. Serial Wire Debug pin description Pin Name Type Description SWCLK Input Serial Wire Clock. This pin is the clock for debug logic when in the Serial Wire Debug mode (SWDCLK).
UM10375 NXP Semiconductors Chapter 22: LPC13xx Serial Wire Debug (SWD) LPC1xxx VTREF SWDIO SWDIO SWCLK SWCLK RESET nSRST PIO0_1 ISP entry The VTREF pin on the SWD connector enables the debug connector to match the target voltage. Fig 66. Connecting the SWD pins to a standard SWD connector UM10375 All information provided in this document is subject to legal disclaimers.
UM10375 Chapter 23: LPC13xx Supplementary information Rev. 3 — 14 June 2011 User manual 23.1 Abbreviations Table 357. Abbreviations Acronym Description Analog-to-Digital Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture Advanced Peripheral Bus BrownOut Detection Debug Communication Channel Digital Signal Processing End Of Packet Embedded Trace Macrocell GPIO...
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UM10375 NXP Semiconductors Chapter 23: LPC13xx Supplementary information 3.10.3 Using the general purpose counter/timers to Post divider ......49 create a self-wake-up event .
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