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Memory Maps
There are two points of view for memory maps:
1. The mapping of all resources as viewed by local bus masters (local
2. The mapping of onboard resources as viewed by external masters
The memory and I/O maps which are described in the next three tables are
correct for all local bus masters. There is some address translation
capability in the VMEchip2. This allows multiple MVME162LXs on the
same VMEbus with different virtual local bus maps as viewed by different
VMEbus masters.
Local Bus Memory Map
The local bus memory map is split into different address spaces by the
transfer type (TT) signals. The local resources respond to the normal
access and interrupt acknowledge codes.
Normal Address Range
The memory map of devices that respond to the normal address range is
shown in the following tables. The normal address range is defined by the
Transfer Type (TT) signals on the local bus. On the MVME162LX
Embedded Controller, Transfer Types 0, 1, and 2 define the normal
address range. Table 1-4 is the entire map from $00000000 to
$FFFFFFFF. Many areas of the map are user-programmable, and
suggested uses are shown in the table. The cache inhibit function is
programmable in the MC68XX040 MMU. The onboard I/O space must be
marked cache inhibit and serialized in its page table. Table 1-5 further
defines the map for the local I/O devices.
http://www.mcg.mot.com/literature
bus memory map).
(VMEbus memory map).
Memory Maps
1
1-25
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