Introduction; Features - Motorola MC68824 User Manual

SECTION 1
INTRODUCTION
The Motorola MC68824 Token Bus Controller (TBC) is a silicon integrated circuit implementing
the media access control (MAC) portion of the IEEE 802.4 token passing bus standard. IEEE 802.4
defines the physical and MAC portion of the data link layer standards of the Manufacturing
Automation Protocol (MAP) specification.
The TBC simplifies interfacing a microcomputer to a MAP network by providing the link layer
services including managing ordered access to the token bus medium, providing a means for
admission and deletion of stations, and handling fault recovery. Some extra features have been
added to enhance the token bus controller for real time applications. These enhancements consist
of the four levels of priority for transmit and receive and the request with response mechanism.
These features, combined with the basic functionality of the token bus controller, make it ideally
suited for both seven layer MAP networks and the Enhanced Performance Architecture (EPA)
networks defined by MAP version 3.0.
The TBC functions as an intelligent peripheral device to a microprocessor. An on-chip DMA
transfers data frames to and from a buffer memory with minimal microprocessor interface re-
quired. A microcoded fully linked buffer management scheme queues frames during transmission
and reception, and optimizes memory use. This VLSI implementation significantly reduces the
cost of a MAP network.
1.1 FEATURES
The MC68824 provides the following:
• Low Power Consumption through 2 Micron HCMOS Fabrication
• MAC Options Suitable for Real Time Environments
Four Receive and Four Transmit Queues Supporting Four Priority Levels
Immediate Response Mechanism using the Request with Response (RWR) Frame Type
• On-chip Network Monitoring and Diagnostics
• Two Separate Ways of Bridging - Hierarchial and IBM Defined Source Routing
• Powerful Addressing - Group Address Recognition and Multidrop Capability
• System Clock Rate up to 16.67 MHz
• Serial Data Rates from 10 Kbits/Second to 16.67 Mbits/Second
• IEEE 802.4 Recommended Serial Interface Supporting Various Physical Layers
• Simple Interface to Higher Level Software by Means of a Powerful, Fully-Linked Data
Structure
• Highly Integrated M68000 Family Bus Master/Slave Interface
Four Channel DMA for Transfer of Data Frames to and from Memory
40-Byte FIFO to Efficiently Support High Data Rate
32-Bit Address Bus with Virtual Address Capabilities
• Simplified Interface to Other Processor Environments
Byte Swapping Capability for Alternate Memory Structures
8- or 16-Bit Data Bus
MC68824 USER'S MANUAL
MOTOROLA
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