User Leds (Active-High); User Dip Switches (Active-High) And I/O Header - Xilinx Virtex-7 VC7203 User Manual

Chapter 1: VC7203 Board Features and Operation
Table 1-9: SuperClock-2 FPGA I/O Mapping (Cont'd)
FPGA (U1)
Pin Function
C21 Control I/O
D18 Control I/O
D17 Control I/O
F20 Control I/O
E20 Control I/O
K17 Control I/O
J17 Control I/O
J20 CM_RESET

User LEDs (Active-High)

Callout 23,
DS13 through DS20 are eight active-High LEDs that are connected to user I/O pins on the
FPGA as shown in
purpose determined by the user.
Table 1-10: User LEDs
Pin Function
M37 User LED
M38 User LED
R42 User LED
P42 User LED
N38 User LED
M39 User LED
R40 User LED
P40 User LED

User DIP Switches (Active-High) and I/O Header

Callout 25,
The DIP switch SW2 provides a set of eight active-High switches that are connected to user
I/O pins on the FPGA as shown in
any other purpose determined by the user. Six of the eight I/Os also map to 2 x 6 test
header J125 providing external access for these pins (callout 26,
20
Send Feedback
Direction I/O Standard
Output LVCMOS18
Output LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
In/Out LVCMOS18
Output LVCMOS18
Figure 1-2.
Table 1-10 These LEDs can be used to indicate status or any other
FPGA (U1)
Direction
Output
Output
Output
Output
Output
Output
Output
Output
Figure 1-2.
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Schematic
Net Name
Pin
CM_CTRL_17 95
CM_CTRL_18 97
CM_CTRL_19 99
CM_CTRL_20 101
CM_CTRL_21 103
CM_CTRL_22 105
CM_CTRL_23 107
CM_RST 66
Schematic Net
Name
I/O Standard
LVCMOS18 APP_LED1
LVCMOS18 APP_LED2
LVCMOS18 APP_LED3
LVCMOS18 APP_LED4
LVCMOS18 APP_LED5
LVCMOS18 APP_LED6
LVCMOS18 APP_LED7
LVCMOS18 APP_LED8
Table 1-11. These pins can be used to set control pins or
VC7203 GTX Transceiver Characterization Board
J82 Pin
Function Direction
CS0_C3A Input
CS1_C4A Input
NC —
NC —
NC —
NC —
NC —
RESET_B Input
Reference
Designator
DS19
DS20
DS17
DS18
DS16
DS15
DS13
DS14
Figure 1-2.).
UG957 (v1.3) October 17, 2014