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value to the first test offset. It is then verified that the initial data value is still stored at every other
power-of-two offset. If a location is found, other than the one just written, that contains the new
data value, there is a problem with the current address bit. If no overlapping is found, the procedure
is repeated for each of the remaining offsets.
32-Bit Inverse Address Test
This test behaves similarly to the memory test described above, except the addresses are tested in
the inverse direction. This test helps to identify a broader scope of possible addressing errors
inherent in the memory modules.
4.9.4
FPGA Version Check
This test is targeted to verify the correct FPGA image programmed into both FPGA chips. It
displays the FPGA version on both FPGAs. Both versions should be the same. If the programmed
version is older than expected, an event is logged to the SEL.
4.9.5
DS1307 RTC (Real-Time Clock) Test
This test is targeted to verify the functionality of DS1307 RTC chip. This test displays the date/time
settings from the RTC and validates the readings. If any readings are found to be non-BCD format,
an event is logged to the SEL. This test also captures current time, sleeps a while, and compares the
previously captured time and new time. If they differ, it means the RTC is working. If not, an event
is logged to the SEL.
4.9.6
NIC Presence/Local PCI Bus Test
This test generates the PCI bus transaction by scanning the PCI buses available on the board. This
test detects the two Ethernet devices and verifies each device has the valid Vendor ID and Device
ID in the PCI configuration space. NIC internal self-test is not performed here, as the self-test is
executed when loading the Ethernet driver.
4.9.7
OS Image Checksum Test
This test is targeted to verify the OS image stored in the flash is not corrupted. This test calculates
the CRC32 checksum from the OS image, and then compares it with the image checksum stored in
the FIS directory. If one mismatches another, BIST will log an error event to the SEL.
4.9.8
CRC32 Checksum
CRC32 is the 32-bit version of Cyclic Redundant Check technique, which is designed to ensure the
bits validity and integrity within the data. It first generates the diffusion table, which consists of
256 entries of double-word; each entry is known as a unique diffusion code. The checksum
calculation is started by fetching the first byte in data buffer, exclusive-OR with the temporary
checksum value. The resulting value is AND-ed with 0xFF to restrict an index from 0 to 255
(decimal). That index is used to fetch a new diffusion code from the table. Next, the newly fetched
diffusion code is exclusive-OR with the most significant 24 bits of the temporary checksum value
(effectively 8 bits left-shifting the checksum value). The resulting value is the new temporary
checksum value. The calculation process is repeated until the last byte in the data buffer. The final
temporary checksum value becomes the final checksum value.
MPCMM0001 Chassis Management Module Software Technical Product Specification
Download from Www.Somanuals.com. All Manuals Search And Download.
Built-In Self Test (BIST)
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