Src Clock Group; Src Clock Topology; Source Shunt Termination; Scr/Scr# Routing Guidelines - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
11.2.9

SRC Clock Group

11.2.9.1

SRC Clock Topology

The clock synthesizer provides one set of 100-MHz differential clock outputs. The differential
clocks are driven to the Intel
®
Intel 6300ESB I/O Controller Hub for serial-ATA as shown in
The clock driver differential bus output structure is a Current Mode Current Steering output that
develops a clock signal by alternately steering a programmable constant current to the external
termination resistors Rt.
The recommended termination for the differential bus clock is a Shunt Source Termination. See
Figure 146
function, converting the current output of the clock driver to a voltage and matching the driver
output impedance to the transmission line. The series resistors Rs provide isolation from the clock
driver's output parasitics which would otherwise appear in parallel with the termination resistor Rt.
The value of Rt should be 49 Ω and Rs should be 33 Ω . Simulations have shown that Rs values
above 33 Ω provide no benefit to signal integrity but only degrade the edge rate.
Figure 146.

Source Shunt Termination

Clock
Driver
Table 114. SCR/SCR# Routing Guidelines (Sheet 1 of 2)
Trace Width
Differential Pair Spacing
Spacing to Other Traces
Serpentine Spacing
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Pentium
for an illustration of this terminology scheme. Parallel Rt resistors perform a dual
LT = L1 + L2 + L4
Rs
L1
L1'
Rs
Layout Guideline
January 2007
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6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
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M Processor and Embedded Intel
L2
L2'
L3 L3'
Rt Rt
Value
5 mils
11 mils
25 mils
Maintain a minimum 25 mils.
Keep parallel serpentine
sections as short as possible.
Minimize 90-degree bends.
Make 45-degree bends, if
possible.
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855GME Chipset with
Figure 137.
L4
L4'
Intel®
6300ESB
Illustration
Figure 147
Figure 147
Figure 147
Notes
1, 2, 3
261