Ich4-M Power Management Interface; Fwh/Lpc Interface - Intel 855GM Design Manual

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16.7.6.

ICH4-M Power Management Interface

Pin Name
PM_DPRSLPVR
PM_SLP_S1#/GPIO19
PM_SLP_S3#,
PM_SLP_S4#,
PM_SLP_S5#
PM_BATLOW#
PM_CLKRUN#
PM_PWRBTN#
PM_PWROK
PM_RI#
PM_RSMRST#
PM_THRM#
PM_SYSRST#
16.7.7.

FWH/LPC Interface

Pin Name
Pull-up/Pull-down
LPC_AD[3:0]
®
Intel 855GM/855GME Chipset Platform Design Guide
System
Pull-up/Pull-down
10 k Ω pull-up to V3ALWAYS
IF NOT USED
10 k Ω pull-up to Vcc3_3
Weak pull-down to gnd
8.2 k Ω -10 k Ω pull-up to
V3ALWAYS
Weak pull-down to gnd
8.2 k Ω Pull-up to Vcc3_3
If TEMP SENSOR not sued
10 k Ω pull-up to V3ALWAYS
if not actively driven.
System
No extra pull-ups required. Connect straight to FWH/LPC.
Notes
Signal has integrated pull-down in ICH4-M.
Signals driven by ICH4-M.
Pull up is not required if it is used. However, signal must
not float if it is NOT being used
Has integrated pull-up of 18 k Ω – 42 k Ω.
RTC well input requires pull-down to reduce leakage from
coin cell battery in G3. Input must not float in G3.
This signal should be connected to power monitoring logic
and should go high no sooner than 10 ms after both
Vcc3_3 and Vcc1_5 have reached their nominal voltages.
CRB uses 100 K Ω pull-down.
If this signal is enabled as a wake event, it needs to be
powered during a power loss event. If this signal goes low
(active), when power returns the RI_STS bit will be set
and the system will interpret that as a wake event.
RSMRST# is a RTC well input and requires pull-down to
reduce leakage from coin cell battery in G3. Input must not
float in G3.
This signal should be connected to power monitoring logic
and should go high no sooner than 10 ms after both
Vcc3_3 and Vcc1_5 have reached their nominal voltages.
CRB uses 100 K Ω pull-down.
Timing Requirement: See LAN_RST#.
External pull-up not required if connecting to temperature
sensor.
This signal to ICH4-M should not float. It needs to be at
valid level all the time.
Notes
Platform Design Checklist
305