Table of Contents
Advertisement
®
®
LV Intel
Pentium
III Processor 512K Dual Processor Platform
Figure 5. Wired-OR Termination Topology
Table 9.
Wired-OR Values
Item
L0
L1
L2
L3
L4
R1
Please note that the value range for R1 present a set of tradeoffs for flight time and dampening
effects. Choosing a value near the upper end of the range (around 200 Ω) impacts the flight times
the least, but provides minimal dampening. Choosing a value at the lower end of the range (around
100 Ω), provides optimal dampening but has a larger impact on the signal flight times. Intel
recommends a value of 150 Ω ±10% as a reasonable tradeoff between dampening and flight time.
3.4
Simulation Methodology
Analog simulations are recommended for high-speed system bus designs. Start simulations prior to
layout. Pre-layout simulations provide a detailed picture of the working "solution space" that meets
flight time and signal quality requirements. By basing board layout guidelines on the solution
space, the iterations between layout and post-layout simulations can be reduced.
16
Chipset "T" Stub
L0
CPU 0
Min
Max
2.8"
3.4"
2.8"
3.4"
1.70"
2.3"
1.5"
Route to shortest length
Should be as short as possible. Optimal case is to make this value
0"
0.2"
zero, making the L3 stub come after the chipset pin.
The range of values has tradeoffs in flight time and dampening
100 Ω
220 Ω
effects. 150 Ω ±10% is a base recommendation.
L1
L2
L3
L4
Chipset
Notes
CPU 1
V
TT
R1
Design Guide
Advertisement
Table of Contents
