Ddr Ii 400 Embedded Address/Control Topology With Split Termination - Intel 80331 Design Manual

Figure 59.

DDR II 400 Embedded Address/Control Topology With Split Termination

1.8 V
100
ohms
TL10
+/- 5%
+/- 5%
GND
TL0 TL9
TL1
Intel® 80331 I/O Processor Design Guide
TL5
TL5
TL5
TL3
100
ohms
TL5
TL2
Register
TL7
TL4
TL6
TL6
TL7
Memory Controller
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
TL8
SDRAM Pin
119