Power Manager Interface Control Signals - Intel PXA27 Series Design Manual

Clocks and Power Interface
Table 3-1. Clock Interface Signals (Sheet 2 of 2)
CLK_TOUT
CLK_REQ
CLK_EXT
3.2.2

Power Manager Interface Control Signals

The PXA27x processor has an internal power manager unit (PMU) and a set of I/O signals for
communicating with an external power management integrated circuit (PMIC). The I/O signals are
active for initial power-up, certain reset events, device on/off events, and transitions between some
operating modes. There are also two Fault signals (nBATT_FAULT and nVDD_FAULT) required
from the PMIC to communicate the onset of power supply problems to the processor.
The PXA27x processor communicates to the power controller using the signals defined in
Table 3-2.
Table 3-2. Power Controller Interface Signals
Signal
PWR_EN
SYS_EN
PWR_SCL
PWR_SDA
nRESET
nBATT_FAULT
nVDD_FAULT
PWR_CAP<3:0>
PWR_OUT
48_MHz
† Input and Output refers to signal direction to or from the PXA27x processor.
II:3-2
Output Drives a buffered and inverted version of the TXTAL_IN oscillator input.
Input during power-on or hardware reset that indicates whether the processor
oscillator clock input comes from PXTAL_IN (CLK_REQ low) or CLK_PIO
Bidirectional (CLK_REQ floating). If CLK_PIO is the processor oscillator input, CLK_REQ
becomes an output indicating when the processor oscillator is required. For more
information, refer to
Used by the Mobile Scalable Link (MSL), SSP or operating system (OS) timer
Input
module as a clock input (optional).
Definition
Power Enable
System Enable
2
I C bus clock
2
I C bus data
Forces an unconditional hardware
reset
Indicates main battery removed or
discharged
Indicates one or more supplies are out
of regulation
The PWR_CAP pins connect to
external capacitors that are used with
on-chip DC-DC converter circuits to
achieve very low power in sleep
mode.
Connects to an external isolated
capacitor.
48 MHz output clock
Used to generate peripheral timing
from the 312-MHz peripheral clock
Section 3.5.1, "Clock Interface."
Active State
High
High
Clock
—
Low
Low
Low
—
—
Clock
®
Intel PXA27x Processor Family Design Guide
†
Signal Direction
Output
Output
Output
Bidirectional
Input
Input
Input
Analog
Analog
Output