Table of Contents
Advertisement
®
Intel
855GME Chipset and Intel
®
®
Intel
Pentium
M/Celeron
Refer to
Section 4.1.2.1
complementary strobe signals associated with each group shall be length matched (pad-to-pin) to
each other within ± 25 mils and tuned to the average length of the data signals (pad-to-pin) of their
associated group. This optimizes setup/hold time margin.
®
Table 5.
Intel
Pentium
Trace Length Mismatch Mapping
Data Group
D[15:0]#
D[31:16]#
D[47:32]#
D[63:48]#
NOTES:
1. Strobes of the same group shall be trace length matched to each other within ± 25 mils and to the average
length of their associated data signal group.
2. All length matching formulas are based on GMCH die-pad to Intel Pentium M/Celeron M Processor pin
total length per byte lane. Package length tables are provided for all signals to facilitate this pad-to-pin
matching.
Table 6
lists the source synchronous data signal general routing requirements. Due to the 400 MHz,
high-frequency operation the data signals shall be limited to a pin-to-pin trace length minimum of
0.50 inches and maximum of 5.5 inches.
®
Table 6.
Intel
Pentium
Data Signal Routing Guidelines
Signal Names
Data Group #1 Data Group #2
D[15:0]#
D[31:16]#
DINV0#
DINV1#
DSTBN[0]#
DSTBN[1]#
DSTBP[0]#
DSTBP[1]#
4.1.3.2
Source Synchronous – Address Group
Source synchronous address signals operate at 200 MHz. Thus, their routing requirements are very
similar to the data signals. Refer to
details the partition of the address signals into matched length groups. Due to the lower operating
frequency of the address signals, pad-to-pin length matching is relaxed to ± 200 mils. Each group
is associated with only one strobe signal. To maximize setup/hold time margin, the address strobes
shall be trace length matched to the average trace length of the address signals of their associated
group. In addition, each address signal shall be trace length matched within ± 200 mils of its
associated strobe signal.
48
®
6300ESB ICH Embedded Platform Design Guide
®
M Processor FSB Design and Power Delivery Guidelines
for trace length and package compensation requirements. The two
®
®
M/Celeron
M Processor FSB Data Source Synchronous Signal
DINV Signal for
Signal
Associated
Matching
Data Group
DINV0#
± 100 mils
DINV1#
± 100 mils
DINV2#
± 100 mils
DINV3#
± 100 mils
®
®
M/Celeron
M Processor System Bus Source Synchronous
Data Group #3
Data Group #4
D[47:32]#
D[63:48]#
DINV2#
DINV3#
DSTBN[2]#
DSTBN[3]#
DSTBP[2]#
DSTBP[3]#
Section 4.1.3
Data Strobes
Associated with the
Group
DSTBP0#, DSTBN0#
DSTBP1#, DSTBN1#
DSTBP2#, DSTBN2#
DSTBP3#, DSTBN3#
Trans-
mission
Total Trace Length
Line Type
Min
Max
(inches)
(inches)
Strip-line
0.5
5.5
Strip-line
0.5
5.5
Strip-line
0.5
5.5
Strip-line
0.5
5.5
and
Section 4.1.3.1
for further details.
Strobe
Notes
Matching
± 25 mils
1,
2
± 25 mils
1,
2
± 25 mils
1,
2
± 25 mils
1,
2
Width
Nominal
and
Impedance
spacing
( Ω )
(mils)
55 ± 15%
4 and 12
55 ± 15%
4 and 12
55 ± 15%
4 and 12
55 ± 15%
4 and 12
Table 7
Advertisement
Table of Contents
