Qdr Sram Q (Data In) Topology; Q (Data In) Routing Topology; Qdr Q (Data In) Signal Group Routing Guidelines - Intel IXP28XX Manual

IXP28XX Network Processor
QDR SRAM
4.5.4
Figure 32.
Table 23.
70
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QDR SRAM Q (Data In) Topology

For Data Bus to work successfully at 233MHz, especially the READ signal, only x9 SRAM parts
need to be used and not x18 parts for multiple loads. Thus the data bus (READ and WRITE) should
be split in two halves each with a 9bit including the parity bit. The loads for each Data signal must
be maintained at 2 SRAMs only that are clam-shelled together so that they electrically constitute
one load only.
Figure 32 illustrates QDR SRAM Q (Data In) topology.

Q (Data In) Routing Topology

T-Topology
Data-In (Q0 - Q7, Q9 - Q16),
Parity-In (Q8, Q17) Signals
®
Intel
IXP2800 Receiver
Data-in, Parity-in
On-Die Termination
Table 23 provides routing guidelines for the QDR Q (Data In) signal group.

QDR Q (Data In) Signal Group Routing Guidelines

Parameter
Signal Group
Topology
Reference Plane
Characteristic Trace Impedance
RTT
Nominal Trace Width
Nominal Trace Separation
Group Spacing
1
Trace length P +A to SRAMs
Trace length B, C
Maximum via count per signal
Length tuning method
B
A
C
Q
Matched T-topology
Ground
50 Ω ±10%
50 Ω ±1% on-die termination at the IXP28XX receiver
5 mils
8 - 15 mils
Isolation from all other signals is 20 - 25 mils.
Should be matched to CIN-Clk (return clock) trace
length.
Maximum = 11.0 inches
As short as possible. B and C must match.
Maximum B = 0.25 inches
Maximum C= 0.25 inches
As small as possible; Maximum = 7 vias
All Q signals matched within ±25 mils, where length
includes package length compensation (P+A)
QDR Top SRAM
QDR Bottom SRAM
B3955-01
Routing Guideline
Hardware Design Guide