Platform Debug and Test Hooks—Intel
19.0
Platform Debug and Test Hooks
19.1
Platform Debug and Test Hooks General Introduction
19.1.1
Description
Intel is committed to reducing debug time and cost for OEMs and system integrators.
Many debug features and test hooks can be designed into the platform to help reduce
these factors. The following section provides an overview of the Intel
X1000 debug and test hooks.
19.2
Platform Debug Port
JTAG Probe - The Intel
®
Intel
Quark™ SoC X1000-based designs where there is no room to support a 60-pin
Merged XDP connector.
• Keep Out Zone (KOZ) is required around processor.
• JTAG routing on the platform is required.
• Provides access to SoC JTAG signals, processor configuration signals and others.
• Provides access to SoC test interface signals. A Logic Analyzer (LA) connector
footprint is not required.
19.2.1
Signal Routing Guidelines
JTAG signal routing topology requirements are different from previous designs.
Guidelines for routing the JTAG pins can be found in the Intel
Platform - Debug Port Design Guide.
19.3
JTAG Boundary Scan
The SoC includes a JTAG (TAP) port compatible with the IEEE Standard Test Access Port
and Boundary Scan Architecture 1149.1 Specification. The TAP controller is accessed
serially through the five pins TCK, TMS, TDI, TDO, and TRST_B#. Additionally routing
the PRDY_B and PREQ_B to the header would be advantageous from a debug
perspective.
TMS, TDI and TDO operate synchronously with TCK which is independent of all other
clock within the SOC. TRST_B#, per the specification, is an optional signal. This 5-pin
interface can be used for test and debug purposes. System board interconnects can be
DC tested using the boundary scan logic in pads.
19.3.1
Terminating Unused JTAG Signals
When unused, all JTAG pins should be pulled according to the following table.
June 2014
Order Number: 330258-002US
®
Quark™ SoC X1000
®
Quark™ SoC X1000 uses this option to impact the nature of
®
Quark™ SoC
®
Quark™ SoC X1000
®
Intel
Quark™ SoC X1000
PDG
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