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®
Intel
855GME Chipset and Intel
Figure 18. Routing Illustration for Topology 1C
Table 13. Layout Recommendations for Topology 1C
L1
0.5" – 12.0"
0.5" – 12.0"
4.1.5.4
Topology 2A: Open Drain (OD) Signals Driven by AND Gate–
PWRGOOD
The Topology 2A OD signal PWRGOOD, which is driven by an AND gate (Intel Pentium
M/Celeron M processor CMOS signal input), shall adhere to the following routing and layout
recommendations.
of the Intel Pentium M/Celeron M processor. The routing guidelines allow the signal to be routed
as either micro-strip or strip-lines using 55 Ω ± 15 percent characteristic trace impedance. The
pull-up voltage for termination resistor Rtt is VCCP (1.05 V).
illustration for Topology 2A.
Note: The output from the AND Gate (AND of power supply PWRGD_3V and CPU VR__PWRGD)
shall be routed point-to-point to the Intel Pentium M/Celeron M processor's PWRGOOD signal.
The routing from the Intel Pentium M/Celeron M processor's PWRGOOD pin shall fork out to the
termination resistor, Rtt, and the AND gate. Segments L1 and L2 from
from a trace from the Intel Pentium M/Celeron M processor pin.
Figure 19. Routing Illustration for Topology 2A
V
Rtt
CPU
VCCP
Rtt
L2
L1
Rs
L2
L3
L4
0" – 3.0"
0" – 3.0"
0.5" – 12.0"
0" – 3.0"
0" – 3.0"
0.5" – 12.0"
Table 14
lists the recommended routing requirements for the PWRGOOD signal
P
27
L2
January 2007
®
6300ESB ICH Embedded Platform Design Guide
3.3
3.3
R1
Q2
Q1
L3
3904
Rs
R1
330 Ω ± 5%
330 Ω ± 5%
1.3 kΩ ± 5%
330 Ω ± 5%
330 Ω ± 5%
1.3 kΩ ± 5%
Figure 19
PWRGD_3V
L1
PU_VR_PWRGD
(System
receiver)
V_IO_RCVR
R2
L4
3904
Transmission
R2-
Rtt
Line Type
56 Ω ± 5%
Micro-strip
56 Ω ± 5%
Strip-line
depicts the routing
Table 14
shall not T-split
4871-01
61
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