Intel 855GME Design Manual page 79

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Intel 855GME Chipset and Intel 6300ESB ICH Embedded Platform Design Guide
connector's BPM[3:0]# pins to Intel Pentium M/Celeron M processor's BPM[3:0]# pins. Connect
the ITP700FLEX's BPM[4]# signal to the Intel Pentium M/Celeron M processor's PRDY# pin.
The ITP700FLEX's integrated far-end terminations as well as the processor's AGTL+ integrated
on-die termination ensure proper signal quality for the BPM[4:0]# signals. Due to the length of the
ITP700FLEX cable, the length L2 of the BPM[4:0]# signals on the motherboard should be limited
to shorter than 6.0 inches. The BPM[4:0]# signals' length L2 should be length matched to each
other within ± 50 ps. The BPM[4:0]# signal trace lengths are matched inside the Intel Pentium
M/Celeron M processor package, thus motherboard routing does not need to compensate for any
processor package trace length mismatch. The BPM[4:0]# signal lengths also need to be matched
within ± 50 ps to the L3+L4-L5 net lengths of the RESET# signal, i.e., L3 + L4 – L5 = L2 (within
± 50 ps).
Refer to Figure 36 for topology. See below for more details on routing guidelines for the RESET#
signal.
Due to the Intel Pentium M/Celeron M processor's AGTL+ on-die termination for BPM[3:0]# and
PRDY#, there is no issue or concern if the BPM[4:0]# pins of the ITP700FLEX connector are left
floating when the ITP is not being used and the ITP700FLEX cable is unplugged.
Route the ITP700FLEX connector's BPM[5]# signal as a Zo = 55 Ω point-to-point connection to
the Intel Pentium M/Celeron M processor's PREQ# pin. Integrated on the ITP700FLEX BPM[5]#
driver signal is a resistive pull-up that ensures proper signal quality at the processor's PREQ# input
pin. The Intel Pentium M/Celeron M processor has an integrated, weak, on-die pull-up to VCCP
for the PREQ# signal to ensure a proper logic level when the ITP700FLEX port connector is not
plugged in. There is no need for any external termination on the motherboard for the BPM[5]# =
PREQ# signal. The maximum length of BPM[5]#/PREQ# should not exceed 6.0 inches.
As explained in Section 4.1.6, the RESET# signal forks (see Figure 14) out from the 82855GME's
CPURESET# pin and is routed to the Intel Pentium M/Celeron M processor and ITP700FLEX
debug port. One branch from the fork connects to the Intel Pentium M/Celeron M processor's
RESET# pin and the second branch connects to a 220 Ω ± 5 percent termination pull-up resistor to
VCCP placed close to the ITP700FLEX debug port. A series 22.6 Ω ± 1 percent resistor is used to
continue the path to the ITP700FLEX RESET# pin with the RESETITP# net in Figure 36. The
length of the RESETITP# net (labeled as net L4) should be limited to less than 0.5 inches. To
ensure correct operational timings, the length of the RESET# nets L3, L4, and L5 with respect to
the BPM[4:0]# net length L2 should adhere to the following length matching requirement within
± 50 ps., i.e., L3 + L4 – L5 = L2 (within ± 50 ps).
There is no need for pull-up termination on the Intel Pentium M/Celeron M processor side of the
RESET# net due to presence of AGTL+ on-die termination on the processor and the 82855GME.
The ITP700FLEX debug port's BCLKp/BCLKn inputs are driven with a 100 MHz differential
clock from the CK409 clock chip. The CK409 also feeds two other pairs of 100-MHz differential
clocks to the Intel Pentium M/Celeron M processor BCLK[1:0] and Intel 855GME chipset
BCLK[1:0] input pins. Common clock signal timing requirements of the 82855GME and the Intel
Pentium M/Celeron M processor requires matching of processor and GMCH BCLK[1:0] nets L6
and L7, respectively. To ensure correct operation of ITP700FLEX, the BCLKp/BCLKn net L8
should be tuned to within ± 50 ps to the sum of length L6 of the BCLK[1:0] lines and the additional
length L2 of the BPM#[4:0] signals, i.e., L6 + L2 = L8 (within ± 50 ps).
The timing requirements for the BPM[5:0]#, RESET#, and BCLKp/BCLKn signals of the
ITP700FLEX debug port require careful attention to their routing. Standard high-frequency bus
routing practices should be observed.
1. Keep a minimum of 2:1 spacing in between these signals and to other signals.
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