Intel 855GME Design Manual page 73

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Intel 855GME Chipset and Intel
The signals below shall be isolated from the motherboard via specific termination resistors on the
ITP interposer itself according to interposer debug port recommendations. For the case where the
onboard ITP700FLEX debug port is used, refer to
recommendations.
Table 18. ITP Signal Default Strapping When ITP Debug Port Not Used
Signal
TDI
TMS
TRST#
TCK
TDO
Figure 34 illustrates the recommended layout for the Intel Pentium M/Celeron M processor's
strapping resistors. To avoid interaction with Intel Pentium M/Celeron M processor FSB routing,
the TEST[2:1] and RSVD (pin C16) signal resistors are placed on the secondary side of the
motherboard. To avoid GND via interaction with the Intel Pentium M/Celeron M processor FSB
routing, the resistors share GND via connections with the A8, A17, and A20 ground pins of the
Intel Pentium M/Celeron M processor.
The 150 Ω, pull-up resistor to V
of the board. The placement of the strapping resistors for TDI, TMS, TRST#, and TCK is not
critical.
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Figure 34. Intel Pentium
TEST[2]
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Resistor Value Connect To
150 Ω ± 5%
VCCP
39 Ω ± 5%
VCCP
680 Ω ± 5%
GND
27 Ω ± 5%
GND
Open NC
(1.05 V) for TDI is shown in
CCP
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M/Celeron M Processor Strapping Resistor Layout
SECONDARY SIDE
A8, A17 and A20
GND pins
RSRVD C16
January 2007
6300ESB ICH Embedded Platform Design Guide
Section 4.3 for default termination
Resistor Placement
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
Within 2.0" of the CPU
N/A
Figure 34
TDI
TMS
TRST#
TCK
on the secondary side
TEST[1]
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