Dvob And Dvoc Port Flexible (Modular) Design; Dvob And Dvoc Module Design - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Integrated Graphics Display Port
Figure 79. Driver-Receiver Waveforms Relationship Specification
Driver
The setup margin and the hold margin for a particular design depends on the values of the data
valid times and the data setup and hold times on both the driver and the receiver sides. However,
available margins are not absolute values. Any skew due to routing and loading differences, any
coupling differences in the parallel traces, and any effects of SSO (ISI, ground bounce, etc.) shall
be accounted for in the timing budget as they reduce the total available margin for the design.
Table 54. Allowable Interconnect Skew Calculation
Component
Driver
Interconnect
Receiver
All numbers in this table are from the 82855GME specification documents that are applicable for
this interface. For third party receiver devices, refer to appropriate third party vendor
specifications.
6.4

DVOB and DVOC Port Flexible (Modular) Design

The GMCH supports flexible design interfaces described in this section.
6.4.1

DVOB and DVOC Module Design

The 82855GME supports a DVO module design connected to the GMCH through a generic
connector. Simulation method is the same as in
by simulation as L1 = 4 inches and L2 = 2 inches. Refer to
parasitic model.
168
®
6300ESB ICH Embedded Platform Design Guide
Driver
Strobe
Data1 Data2
Data
tDVb
tDVa
Data Delay
Receiver
Strobe
Receiver
Data
Skew Element
Data Valid before Strobe
Data Valid after Strobe
Allowable Skew
Data Setup to Strobe
Data Hold from Strobe
Data3
Data4
Clock Delay
Data3
Data1 Data2
tDSu tDh
Symbol Setup
tDVb 570
tDVa
Vendor Specific Vendor Specific
tDSu Vendor Specific
tDh
Section 6.3.4. Lengths L1 and L2 are determined
Figure 81
Data4
Hold Units
ps
770 ps
ps
ps
Vendor Specific ps
for the generic connector