Intel 855GME Design Manual page 16

®
Intel 855GME Chipset and Intel
Tables
1 Conventions and Terminology .................................................................................................... 21
2 Reference Documents ................................................................................................................ 23
®
3 Intel Pentium
Common Clock Signal Internal Layer Routing Guidelines.......................................................... 40
®
4 Intel Pentium
Signal Package Lengths and Minimum Board Trace Lengths.................................................... 42
®
5 Intel Pentium
Trace Length Mismatch Mapping ............................................................................................... 48
®
6 Intel Pentium
Data Signal Routing Guidelines.................................................................................................. 48
®
7 Intel Pentium
Signal Trace Length Mismatch Mapping .................................................................................... 49
®
8 Intel Pentium
Address Signal Routing Guidelines ............................................................................................ 49
®
9 Intel Pentium
FSB Signal Package Lengths ..................................................................................................... 50
10 Asynchronous AGTL+ Nets ........................................................................................................ 58
11 Layout Recommendations for Topology 1A ............................................................................... 59
12 Layout Recommendations for Topology 1B ............................................................................... 60
13 Layout Recommendations for Topology 1C ............................................................................... 61
14 Layout Recommendations for Topology 2A ............................................................................... 62
15 Layout Recommendations for Topology 2B ............................................................................... 62
16 Layout Recommendations for Topology 3 .................................................................................. 63
17 Processor RESET# Signal Routing Guidelines with ITP700FLEX Connector ........................... 65
18 ITP Signal Default Strapping When ITP Debug Port Not Used .................................................. 73
19 Recommended ITP700FLEX Signal Terminations ..................................................................... 80
20 VCCA[3:0] Decoupling Guidelines.............................................................................................. 88
®
21 Intel Pentium
®
22 Intel Pentium
23 DDR Power-Up Initialization Sequence .................................................................................... 107
24 GMCH Decoupling Recommendations..................................................................................... 108
25 Analog Supply Filter Requirements .......................................................................................... 117
26 Power Signal Decoupling ......................................................................................................... 121
®
27 Intel 855GME Chipset DDR Signal Groups............................................................................ 123
28 Length Matching Formulas ....................................................................................................... 124
29 Clock Signal Mapping ............................................................................................................... 125
30 DDR Clock Signal Group Routing Guidelines .......................................................................... 126
31 DDR Clock Package Lengths ................................................................................................... 130
32 Data Signal Group Routing Guidelines..................................................................................... 132
33 SDQ/SDM to SDQS Mapping ................................................................................................... 135
34 DDR SDQ/SDM/SDQS Package Lengths ................................................................................ 137
35 Control Signal to DIMM Mapping.............................................................................................. 138
36 Control Signal Routing Guidelines............................................................................................ 140
37 Control Group Package Lengths .............................................................................................. 142
38 Command Topology Routing Guidelines .................................................................................. 143
39 Command Group Package Lengths ......................................................................................... 146
40 Control Signal to DIMM Mapping.............................................................................................. 146
41 CPC Control Signal Routing Guidelines ................................................................................... 148
16
®
6300ESB ICH Embedded Platform Design Guide
® ®
M/Celeron M Processor System Bus
® ®
M/Celeron M Processor and Intel
® ®
M/Celeron M Processor FSB Data Source Synchronous Signal
® ®
M/Celeron M Processor System Bus Source Synchronous
® ®
M/Celeron M Processor FSB Address Source Synchronous
® ®
M/Celeron M Processor FSB Source Synchronous
® ®
M/Celeron M Processor and GMCH Source Synchronous
® ®
M/Celeron M Processor VCC-CORE Decoupling Guidelines ........................ 95
® ®
M/Celeron M Processor VCCP Decoupling Guidelines................................ 101
®
GMCH FSB Common Clock