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®
Intel
855GME Chipset and Intel
12.3.1.3
DIMM Decoupling Recommendation Checklist
Table 123
Table 123. DIMM Decoupling Recommendation Checklist
Pin Name
V_1P25_MEMVTT
V_2P5_SM
† Used on Intel CRB.
12.3.2
Frontside Bus (FSB) Checklist
Table 124
and HYSWING reference voltage generation circuit.
Table 124. FSB Checklist (Sheet 1 of 2)
Pin Name
ADS#
HTRDY#
DRDY#
DEFER#
HITM#
HIT#
HLOCK#
BREQ0#
BNR#
BPRI#
DBSY#
RS[2:0]#
HA[31:3]#
HREQ[4:0]#
HADSTB[1:0]#
presents the DIMM decoupling recommendation checklist.
F
Qty
0.1 µF
(55
†
4.7 µF
470 µF
0.1 µF
9 (15
100-150 µF
†
(220 µF
)
(3
†
(100 µF
)
(1
presents the FSB Checklist.
System
Pull-up/Pull-down
January 2007
®
6300ESB ICH Embedded Platform Design Guide
Place one 0.1 µF cap close to every two pull-up
resistors terminated to V_1P25_MEMVTT (VTT for
†
)
DDR signal termination). Place two 4.7 µF caps at either
3
end of the VTT island and one near the center. Four
4
470 µF capacitors may be placed as bulk decoupling.
Refer to
Section 4.8.1.3
†
)
A minimum of nine high frequency caps are
4
recommended to be placed between the DIMMS.
†
A minimum of four low frequency caps are required.
)
Refer to section
Section 4.8.3.2
†
)
Figure 151
depicts the Intel
Connect directly to processor (ADS# signal).
Connect directly to processor (TRDY# signal).
Connect directly to processor (DRDY# signal).
Connect directly to processor (DEFER# signal).
Connect directly to processor (HITM# signal).
Connect directly to processor (HIT# signal).
Connect directly to processor (LOCK# signal).
Connect directly to processor (BR0# signal).
Connect directly to processor (BNR# signal).
Connect directly to processor (BPRI# signal).
Connect directly to processor (DBSY# signal).
Connect directly to processor (RS[2:0]# signals).
Connect directly to processor (A[31:3]# signals).
Connect directly to processor (REQ[4:0]# signals).
Connect directly to processor (ADSTB[1:0]# signals).
Schematic Checklist Summary
Notes
for more information.
for more information.
®
855GME Chipset HXSWING
Notes
√
√
275
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