Dual Channel Source Synchronous Signal Group Routing - Intel Xeon Design Manual

Intel
Figure 9. 1-DIMM per Channel Implementation
Figure 10. 2-DIMMs per Channel Implementation
3.2.1

Dual Channel Source Synchronous Signal Group Routing

Table 8 states the routing requirements for the DQ, DQS and CB signals. All signals in a data group
must be length matched to the associated DQSs, as described in the Intel
®
Intel E7500/E7501 Chipset Compatible Platform Design Guide. Length matching past the last
DIMM connector is not critical. Route all data signals and their associated strobes on the same
layer. Try to maintain routing the signals on the same layer. When a layer transition must occur,
minimize the discontinuity in the ground reference plane. The source synchronous signals require
series termination resistors (Rs) placed close to the first DIMM connector, and parallel termination
resistors (Rtt) placed after the last DIMM connector. These solutions do not require DQS to
CMDCLK pair length matching.
When resistor packs are used for the termination resistors, it is suggested that data group signals
not be mixed with Source Clocked, Chip Select, or Clock Enable signals within the same resistor
pack for purposes.
Platform Design Guide Addendum
®
Xeon™ Processor and Intel
MCH
MCH
SMBus Address:
Command Clock:
Chip Select:
®
E7500/E7501 Chipset Compatible Platform
D
I
M
M
B1 A1
SMBus Address: 04h 00h
Command Clock: 0/0# 0/0#
Chip Select: 0/1 0/1
Fill Second Fill First
D D D
I I I
M M M
M M M
B1 A1 B2
04h 00h 05h
0/0# 0/0# 1/1#
0/1 0/1 2/3
D
I
M
M
D
I
M
M
A2
01h
1/1#
2/3
®
Xeon™ Processor and
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