General Routing And Placement; Lpc Trace Length Matching; Lpc Interface Routing Guidelines - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
®
Intel 6300ESB Design Guidelines
All the other signals have the same name on the 6300ESB and on the LPC Interface.
Figure 114. LPC Interface Diagram
Intel
9.7.1

General Routing and Placement

Use the following general routing and placement guidelines when laying out a new design.
1. LPC signals should be ground referenced.
2. Route all traces using microstrip or stripline over continuous planes (Vcc or GND), with no
interruptions. Avoid crossing over anti-etch if at all possible. Any discontinuity or split in the
ground plane may cause signal reflections and should be avoided.
3. Route LPC signals using a minimum of vias and corners. This reduces reflections and
impedance changes.
4. No 90 degree bends or stubs.
9.7.2

LPC Trace Length Matching

LPC clock traces should be trace length matched. Max trace length mismatch between clocks
coming from the clock driver should be no greater that 250 mils.
9.7.3

LPC Interface Routing Guidelines

Figure 115. LPC Interface Topology
Intel
I/O Controller
220
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6300ESB ICH Embedded Platform Design Guide
PCI Bus
LAD[3:0]
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6300ESB
ICH LFRAME#
LDRQ#
(optional)
LPCPD#
SUS_STAT#
(optional)
LSMI#
GPI
(optional)
L1
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6300ESB
Hub
PCI PCI
CLK RST#
Super I/O
LPC Interface
L2
L3
PCI
PCI
SERIRQ
PME#
LPC_RCVR1
LPC_RCVR2
B1842-02