Ddr Layout Guidelines; Source Synchronous Signal Group; X64 Ddr Memory Configuration; X72 Ddr Memory Configuration - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
7.4

DDR Layout Guidelines

The following sections provide layout information for 80331 DDR333 configuration.
7.4.1

Source Synchronous Signal Group

The guidelines below are for the source synchronous signal group which includes Data bits DQ,
check bits CB, data mask DM, and DQS associated strobe.
The 80331 source synchronous signals are divided into groups consisting of data bits DQ and
check bits CB. There is an associated strobe DQS for each DQ, DM and CB group. When data
masking is not used system memory DM pins on the DDR needs to be tied to ground. The grouping
is as follows for the different memory configurations:
Table 32.

x64 DDR Memory Configuration

Table 33.

x72 DDR Memory Configuration

72
Data Group
DQ[7:0], DM[0]
DQ[15:8], DM[1]
DQ[23:16], DM[2]
DQ[31:24], DM[3]
DQ[39:32], DM[4]
DQ[47:40], DM[5]
DQ[55:48], DM[6]
DQ[63:56], DM[7]
Data Group
DQ[7:0], DM[0]
DQ[15:8], DM[1]
DQ[23:16], DM[2]
DQ[31:24], DM[3]
DQ[39:32], DM[4]
DQ[47:40], DM[5]
DQ[55:48], DM[6]
DQ[63:56], DM[7]
CB[7:0] , DM[8]
Associated Strobe
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
Associated Strobe
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
DQS8