Intel ® Pentium ® M/Celeron ® M Processor Fsb Design And Power Delivery Guidelines; Intel ® Pentium ® M/Celeron ® M Processor Fsb Design Recommendations; Recommended Stack-Up Routing And Spacing Assumptions; Trace Space To Trace - Reference Plane Separation Ratio - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Intel Pentium
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Intel Pentium
Processor FSB Design and Power
Delivery Guidelines
The following layout guidelines support designs using the Intel
Processor and the Intel
on-die Rtt resistors on both the processor and the chipset, additional resistors do not need to be
placed on the motherboard for most Intel Pentium M/Celeron M Processor FSB signals. A simple
point-to-point interconnect topology is used in these cases.
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4.1 Intel
Design Recommendations
For proper operation of the Intel Pentium M/Celeron M Processor and the Intel 855GME chipset, it
is necessary that the system designer meet the timing and voltage specification of each component.
The following recommendations are Intel's best guidelines based on extensive simulation and
experimentation that make assumptions, which may be different from an OEM's system design.
The most accurate way to understand the signal integrity and timing of the Intel Pentium
M/Celeron M Processor FSB in your platform is by performing a comprehensive simulation
analysis. It is possible that adjustments to trace impedance, line length, termination impedance,
board stack-up, and other parameters may be made that improve system performance.
Refer to the latest Intel
90nm Process with 2MB L2 Cache Datasheet, or Intel
FSB signal list, signal types, and definitions. Below are the design recommendations for the data,
address, and strobes. For the following discussion, the pad is defined as the attach point of the
silicon die to the package substrate. The following topology and layout guidelines are preliminary
and subject to change. The guidelines are derived from empirical testing with GMCH package
models.
4.1.1 Recommended Stack-Up Routing and Spacing
Assumptions
The following section describes in more detail, the terminology and definitions used for different
routing and stack-up assumptions that apply to the recommended motherboard stack-up shown in
Section 3.1.
4.1.1.1 Trace Space to Trace – Reference Plane Separation Ratio
Figure 3 illustrates the recommended relationship between the edge-to-edge trace spacing (2X)
versus the trace to reference plane separation (X). An edge-to-edge trace spacing (2X) to
trace – reference plane separation (X) ratio of 2:1 ensures a low crosstalk coefficient. All the
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M/Celeron M Processor FSB Design and Power Delivery Guidelines
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M/Celeron
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855GME chipset Graphics Memory Controller Hub (82855GME). Due to
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Pentium M/Celeron
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Pentium M Processor Datasheet, Intel
January 2007
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6300ESB ICH Embedded Platform Design Guide
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M
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M Processor FSB
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Celeron
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Pentium M/Celeron M
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Pentium M Processor on the
M Processor Datasheet for a
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