Ck409 Clock Checklist; Connection Recommendations - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Schematic Checklist Summary
Table 119. VCC (CORE) Decoupling Recommendations (Sheet 2 of 2)
Option
#3
#4
(Note 1)
NOTES:
1. Decoupling guidelines are recommendations based on Intel reference board design. The Intel Customer
Reference Board uses option #4. This is the preferred recommendation for decoupling.
2. When deciding on overall decoupling solution, customers may need to take layout and PCB board design
into consideration.
3. Option #4 is to be used with small footprint (100 mm
12.2

CK409 Clock Checklist

12.2.1

Connection Recommendations

Table 120
Table 120. CK409 Connection Recommendations (Sheet 1 of 2)
Pin Name
3V66_[0]
3V66_[1]*
3V66_[4:2]
CPU[0], CPU[0]#
CPU[1], CPU[1]#
CPU[2], CPU[2]#
270
®
6300ESB ICH Embedded Platform Design Guide
Description
Low Frequency Decoupling (Polymer
Covered Aluminum – SP Cap, A0
Cap)
Low Frequency Decoupling
(1206 MLCC, >= X5R)
Mid Frequency Decoupling
(0612 MLCC, >= X5R)
Low-Frequency Decoupling (Polymer
Covered Aluminum – SP CAP, AO
Cap)
Mid-Frequency Decoupling
(0805 MLCC>= X5R)
presents the CK409 connection recommendations.
System
Pull-up/Pull-down
49.9 Ω ± 1%
pull- down to GND
C, μ F ESR, m Ω
15 m Ω (max)/5
5 x 330 µF
5 m Ω (typ)/25
25 x 10 µF
5 m Ω (typ)/15
15 x 2.2 µF
4 x 220 μ F 12 m Ω (max)/4
35 x 10 μ F 5 m Ω (typ)/35
2 or less) 0.36 µH ± 20% inductors.
Series
Resistor
When the signal is used, one 33 ohm series
resistor is required. When the signal is NOT
used, it shall be left as NC (Not Connected)
or connected to a test point.
33 Ω ± 5%
*Two possible topologies for 3V66_1:
• Use directly for GMCH's DREFSSCLK.
• Use as input to an SSC device with SSC
output to GMCH's DREFSSCLK.
The Intel CRB routes 3V66[2] (pin 21) to
GCLKIN on GMCH. The other two signals
33 Ω ± 5%
route to 6300ESB (CLK66) and AGP
connector (AGPCLK).
Use one pair for the
pair for GMCH. When onboard ITP is
implemented, the third pair of clock signals
is used for the ITP connector. Otherwise, it
33 Ω ± 5%
may be routed to the dedicated ITP clock
pins on the processor socket.
Refer to Chapter 11
requirements.
√
ESL, nH
3.5 nH/5
1.2 nH/25
0.2 nH/15
3.5 nH/4
0.6 nH/35
√
Notes
processor
and another
for all routing