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®
Intel
855GME Chipset and Intel
Schematic Checklist Summary
Table 133.
PCI Interface Checklist (Sheet 2 of 3)
Checklist Items
PERR#, PLOCK#
PME#
SERR#, STOP#,
TRDY#
PIRQ[H:E]#/
GPIO[5:2]
286
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
Recommend an 8.2 K Ω pull-up
3.3 or a 2.7 Ω K pull-
resistor to V
CC
up resistor to V
5.
CC
No extra pull-up needed.
Recommend an 8.2 K Ω pull-up
3.3 or a 2.7 K Ω pull-
resistor to V
CC
up resistor to V
5.
CC
Recommend a 2.7 K Ω pull-up
5 or 8.2 K Ω resistor
resistor to V
CC
to V
3.3.
CC
Interface not used
Recommend an 8.2 K Ω
pull-up resistor to V
3.3
CC
or a 2.7 K Ω pull-up resistor
to V
5.
CC
May leave as no connect.
Recommend an 8.2 K Ω
pull-up resistor to V
3.3
CC
or a 2.7 K Ω pull-up resistor
to V
5.
CC
Recommend a 2.7 K Ω
pull-up resistor to V
5 or
CC
8.2 K Ω resistor to V
3.3.
CC
Reason/Impact
See PCI 2.2
Component
Specification pull-up
recommendations for
V
3.3 and V
5.
CC
CC
PME# is in the
Resume power plane
and has an internal
pull-up resistor. See
sectionSection 9.10.4
for PME# wiring
recommendations.
See PCI 2.2
Component
Specification pull-up
recommendations for
V
3.3 and V
5.
CC
CC
In Non-APIC Mode,
the PIRQx# signals
may be routed to
interrupts 3, 4, 5, 6, 7,
9, 10, 11, 12, 14 or 15
as described in
Section
9.9.2.
Each PIRQx# line has
a separate Route
Control Register. (See
the 6300ESB EDS for
more information.)
In APIC mode, these
signals are connected
to the internal I/O
APIC in the following
fashion:
• PIRQ[E]# is
connected to
IRQ20
• PIRQ[F]# is
connected to
IRQ21
• PIRQ[G]# is
connected to
IRQ22
• PIRQ[H]# is
connected to
IRQ23
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