Usbclk Clock Group; Usbclk Clock Topology - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Platform Clock Routing Guidelines
11.2.8

USBCLK Clock Group

The 48 MHz USBCLK is series terminated and routed point-to-point on the motherboard. This
clock operates independently and is not length tuned to any other clock.

USBCLK clock topology.

Figure 145. USBCLK Clock Topology
CK409
Table 113. USBCLK Clock Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2
Total Length Range – L1 + L2
Length Matching Required
Breakout Exceptions
260
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6300ESB ICH Embedded Platform Design Guide
Table 113 presents the USBCLK clock routing constraints.
L1
Parameter
Rs
L2
Definition
USBCLK
Individual Net
Series Terminated Point to Point
Ground Referenced
55 Ω ± 15%
4.0 mils
5.0 mils (pin escapes only)
20 mils
4
33 Ω ± 5%
Up to 500 mils
3.0" to 12.0"
3.0" to 12.5"
No
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
Figure 145 depicts the
GMCH