Dotclk Clock Group; Dotclk Clock Topology - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Platform Clock Routing Guidelines
11.2.6

DOTCLK Clock Group

The 48 MHz DOTCLK is series terminated and routed point-to-point on the motherboard. This
clock operates independently and is not length-tuned to any other clock.

DOTCLK clock topology.

Figure 143. DOTCLK Clock Topology
CK409
Table 111. DOTCLK Clock Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2
Total Length Range – L1 + L2
Length Matching Required
Breakout Exceptions
NOTE: The DOTCLK is used internally by the GMCH to generate the pixel clock and must exhibit very low
jitter. Care should be taken to avoid routing through noisy areas and spacing rules should be
observed. Guard traces may be employed if necessary with ground stake vias on no less than
0.5- inch intervals.
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6300ESB ICH Embedded Platform Design Guide
Table 111 presents the DOTCLK clock routing constraints.
L1
Parameter
Rs
L2
Definition
DOTCLK
Individual Net
Series Terminated Point to Point
Ground Referenced
55 Ω ± 15%
4.0 mils
5.0 mils (pin escapes only)
25 mils
4
33 Ω ± 5%
Up to 500 mils
2.0" to 8.0"
2.0" to 8.5"
No
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
Figure 143 depicts the
GMCH