Power Delivery Guidelines - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Figure 52. DDR Power Delivery Block Diagram
Note: +V_1.25 may optionally be on the switch rail and turned off in either S3 or S4. This is only a block
diagram. It is the responsibility of the system designer to ensure that the timing requirements for
the DDR memory devices and GMCH are met.
4.8.2.1 2.5 V Power Delivery Guidelines
The 2.5 V power for the GMCH system memory interface and the DDR DIMMs is delivered
around the DDR command, control, and clock signals. Special attention must be paid to the 2.5 V
copper flooding to ensure proper GMCH and DIMM power delivery. This 2.5 V flood must extend
from the GMCH 2.5 V power vias all the way to the 2.5 V DDR voltage regulator and its bulk
capacitors. The 2.5 V DDR voltage regulator must connect to the 2.5 V flood with a minimum of
six vias. The DIMM connector 2.5 V pins as well as the GMCH 2.5 V power vias must connect to
the 2.5 V copper flood.
In the areas where the copper flooding necks down around the GMCH make sure to keep these
neck down lengths as short as possible. The 2.5 V copper flooding under the DIMM connectors
must encompass all the DIMM 2.5 V pins and must be solid except for the small areas where the
clocks are routed within the DIMM pin field to their specified DIMM pins.
Note: A minimum of 12 mil isolation spacing shall be maintained between the copper flooding and any
signals on the same layer.
Table 25
and termination voltages. For convenience, tolerances are given in both percentage and volts,
although validation shall be done using the specifications exactly as they are written. When the
110
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6300ESB ICH Embedded Platform Design Guide
+V5
Vin
50 - 150 Ω
50 - 150 Ω
+V5
Vin
depicts the voltage and current specifications for each the GMCH and memory reference
Switching
Regulator
Vout
Sense Adj.
Switching
Regulator
Vout
Sense Adj.
+V2_5
+
SMVREF
-
+V1_25