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®
Intel
855GME Chipset and Intel
®
Table 149. Intel
855GME Chipset GMCH Layout Checklist (Sheet 5 of 6)
Checklist Items
GCLKIN
RSTIN#
HLRCOMP
HLVREF
PSWING
HXRCOMP
HYRCOMP
HDVREF[2:0]
HAVREF
HCCVREF
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
• Place series resistor close to CK409,
within 500 mils.
• Total trace length range is 4 to 9 inches.
• Minimum spacing 20 mils.
• Overall length of CLK66 is considered the
reference length for all other CLK66 and
CLK33, except USBCLK and CLK14.
• The length of CLK66 traces should be
matched within ± 100 mils and then used
as the basis for defining the length of all
other length matched clocks.
• Connect to PCIRST# output of the
6300ESB.
GMCH Decoupling, VREF, and Filtering
• GMCH HLRCOMP signal should be
strapped to 1.2 V via 27.4 Ω ± 1%
HLRCOMP resistor with trace impedance
55 Ω ± 15%.
• HLVREF and PSWING voltage
requirements must be set appropriately for
proper hub interface operation. The case
is similar for HIREF and HIVSWING
signals on 6300ESB.
• Each signal should be pulled to ground
with a 27.4 Ω ± 1% resistor.
• Max trace length to the resistor should be
less than 0.5 inches and should be 18 mils
wide to achieve the characteristic
impedance target of 27.4 Ω .
• Maintain 25 mil separation from any
switching signals.
• Max length from pin to voltage divider for
each reference voltage should be less
than 0.5 inches.
• 10 mil traces are recommended.
January 2007
Layout Checklist
Comments
• Refer to CLK66 clock group routing
guidelines detailed in
Section
• Refer to
Section 8.1.4
for HI specific
voltage requirements and several
options for voltage divider circuits.
• This signal is used to calibrate the
Host AGTL+ I/O buffers
characteristics to specific board
characteristics.
• Refer to
Section 4.8.3.2
for more
information.
• To provide constant and clean power
delivery to the data, address, and
common clock signals of the host
AGTL+ interface.
• Refer to
Section 4.8.3.1
for
recommended individual voltage
divider circuits.
11.2.1.
311
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