Sscclk Clock Group - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
11.2.7

SSCCLK Clock Group

The 48/66 MHz SSCCLK operates independently and is not length tuned to any other clock. This
clock employs a spread-spectrum device in its path to reduce EMI. The overall clock path is
divided into two segments as shown in
point-to-point.
Figure 144. SSCCLK Clock Topology
CK409
Table 112. SSCCLK Clock Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2
Trace Length Limits – L3
Trace Length Limits – L4
Total Length Range – L1 + L2 + L3 + L4
Length Matching Required
Breakout Exceptions
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Figure
Table 112 presents the SSCCLK clock routing constraints.
Rs
L1
Parameter
January 2007
6300ESB ICH Embedded Platform Design Guide
Platform Clock Routing Guidelines
144, with each segment series terminated and routed
L2 SSC
Rs
L3
SSCCLK
Individual Net
Series Terminated Point to Point
Ground Referenced
55 Ω ±15%
4.0 mils
5.0 mils (pin escapes only)
20 mils
4 (per driver/receiver path)
33 Ω ±5%
Up to 500 mils
1.0" to 4.0"
Up to 500 mils
1.0" to 7.0"
3.0" to 8.5"
No
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
GMCH
L4
Definition
259