Intel 855GME Design Manual page 94

®
Intel 855GME Chipset and Intel
Note: The 0805 capacitors have V
similar to the 220 µF SP capacitors to achieve a low inductance connection.
The motivation for concentrating the majority of the 0805 mid/high-frequency decoupling
capacitors and all of the SP-type bulk decoupling capacitors on the secondary side layer is to take
advantage of the V
decoupling capacitors. On the primary side, the dog bone via connections for the V
and ground pins effectively separate the V
strips separated by alternating Vss dog bones. These narrow floods that feed the inner V
pins of the processor are non-ideal and for this reason, robust connections to capacitors are
performed on the secondary side. Only three of the mid-frequency decoupling capacitors need to be
placed on the primary side.
Table 21
M/Celeron M processor's VCC_CORE voltage rail. All the decoupling solutions are optimized to
meet the Intel
motherboard layout is used, all four options may result in comparable electrical performance.
However, when comparing all four options, option 4 is the recommended V
solution for Intel Pentium M/Celeron M processor-based systems. Option 4 offers the benefits of
robust electrical performance, comparable efficiency, minimal cost, minimal motherboard surface
area requirements, and lowest acoustic noise. Option 4 is a polymer-covered aluminum and
ceramic-decoupling capacitor based solution that implements four polymer-covered aluminum (SP
type) capacitors that have a low ESR of 12 m Ω each. It also uses 35 x 10 µF 0805 MLCC
mid-frequency decoupling capacitors. Substitution of the 0805 capacitors with 1206 or other
capacitors with higher inductance is not allowed. The other three V
listed below:
In option 1, bulk decoupling is done with 12 x 150 µF polymer-covered tantalum capacitors
(POSCAP type) and mid-frequency decoupling requires the use of 15 x 2.2 µF 0612 MLCC
capacitors characterized by ~0.2 nH inductance (if correct layout is used).
Note: In this case, 1206 form factor capacitors cannot be substituted because their 1.2 nH inductance
value is too high (6x higher than for 0612 capacitors). Though it may result in good electrical
performance when implemented with a correct layout, option 1 occupies more area than the
alternative options.
Option 2 uses purely ceramic decoupling capacitors, employing 40 x 10 µF 1206 MLCC capacitors
as bulk decoupling and 15 x 2.2 µF 0612 MLCC capacitors. The layout for option 2 may be more
difficult to implement when compared to option 4 due to the large 1206 form factor capacitors and
the challenge in making a robust connection using 0612 capacitors. To achieve a surge-free
transient response, option 2 needs to use 0.2 µH inductors that consequently lead to high ripple
current and lower efficiency than the other solutions.
Option 3 uses five polymer-covered aluminum (SP type) capacitors that have a very low ESR of
15 m Ω so that only five such capacitors are required. It also uses 25 x 10 µF 1206 and 15 x 2.2 µF
0612 mid-frequency decoupling capacitors. Substitution of 0612 form factor capacitors with other
form factor capacitors with higher ESL ratings is not allowed. Option 3 is similar to option 4 but it
requires more motherboard area and has higher cost associated with it.
94
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6300ESB ICH Embedded Platform Design Guide
CC-CORE
corridor that establishes a robust connection from the VRM feed to the
CC-CORE
lists four possible decoupling solutions recommended by Intel for the Intel Pentium
® IMVP-IV dynamic tolerance specifications for a load line of 3 m Ω . When a correct
and ground vias on both negative and positive terminals
plane flood into multiple relatively narrow
CC-CORE
CC-CORE
CC-CORE
decoupling
CC-CORE
decoupling options are
CC-CORE
pins