Topology 2B: Cmos Signals Driven By 6300Esb-Lint0/Intr, Lint1/Nmi, A20M#, Ignne#, Slp#, Smi#, And Stpclk; Topology 3: Cmos Signals Driven By 6300Esb To Cpu And Fwh - Init; Routing Illustration For Topology 2B; Layout Recommendations For Topology 2A - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Table 14. Layout Recommendations for Topology 2A
L1
0.5" – 12.0"
0.5" – 12.0"
4.1.5.5 Topology 2B: CMOS Signals Driven by 6300ESB-LINT0/INTR,
LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and STPCLK#
The Topology 2B CMOS LINT0/INTR, LINT1/NMI, A20M#, IGNNE#, SLP#, SMI#, and
STPCLK# signals shall implement a point-to-point connection between the 6300ESB and the Intel
Pentium M/Celeron M processor. The routing guidelines allow both signals to be routed as either
micro-strip or strip-lines using 55 Ω ± 15 percent characteristic trace impedance. No additional
motherboard components are necessary for this topology.
and Table 15
Figure 20. Routing Illustration for Topology 2B
Table 15. Layout Recommendations for Topology 2B
0.5" – 12.0"
0.5" – 12.0"
4.1.5.6 Topology 3: CMOS Signals Driven by 6300ESB
to CPU and FWH – INIT#
The signal INIT# shall adhere to the following routing and layout recommendations.
the recommended routing requirements for the INIT# signal of the 6300ESB. The routing
guidelines allow both signals to be routed as either micro-strip or strip-lines using 55 Ω ± 15
percent characteristic trace impedance.
providing voltage translation between the 6300ESB's INIT# voltage signaling level and any
firmware hub (FWH) that utilizes a 3.3 V interface voltage (shown as a supply V_IO_FWH). Refer
to Section 4.1.5.7
topology and required transistors and resistors for the voltage translator are shown in
Series resistor Rs is a component of the voltage translator logic circuit and serves as a driver
isolation resistor. Rs is shown separated by distance L3 from the first bipolar junction transistor
(BJT), Q1, to emphasize the placement of Rs with respect to Q1. The placement of Rs a distance of
L3 before the Q1 BJT is a specific implementation of the generalized voltage translator circuit
shown in
Table 16. Rs must be placed at the beginning of the T-split of the trace from 6300ESB's INIT# pin.
62
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6300ESB ICH Embedded Platform Design Guide
L2
0" – 3.0"
0" – 3.0"
presents the layout recommendations for Topology 2B.
CPU
L1 Transmission Line Type
Micro-strip
Strip-line
for more details on the voltage translator circuit. For convenience, the entire
Figure 22. The routing recommendations of transmission line L3 in
Rtt Transmission Line Type
330 Ω ± 5%
330 Ω ± 5%
Figure 20
Intel
6300ESB
L1
Figure 21 depicts the recommended implementation for
Micro-strip
Strip-line
depicts the routing illustration
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Table 16
Figure 21.
Figure 21 are listed in
lists