Intel ® Pentium ® M/Celeron ® M Processor And Intel ® 855Gme Chipset; Gmch (82855Gme) Fsb Signal Package Lengths; Signal Trace Length Mismatch Mapping; Address Signal Routing Guidelines - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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Intel Pentium
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Table 7. Intel Pentium

Signal Trace Length Mismatch Mapping

CPU Signal Name
REQ[4:0]#, A[16:3]#
A[31:17]#
NOTES:
1. ADSTB[1:0]# shall be trace length matched to the average length of the associated address signals group.
2. Each address signal shall be trace length matched to its associated address strobe within ± 200 mils.
3. All length matching formulas are based on GMCH die-pad to Pentium M/Celeron M processor pin total
length per signal group. Package length tables are provided for all signals to facilitate this pad to pin
matching.
Table 8 lists the source synchronous address signals general routing requirements. They should be
routed to a pin-to-pin length minimum of 0.50 inches and a maximum of 6.5 inches. Due to the
200 MHz, high-frequency operation of the address signals, the routing guidelines listed in
allow for 2:1 spacing for the address signals given a 55 Ω ± 15% characteristic trace impedance
except for address strobe signals. But if space permits, 3:1 spacing is strongly advised for these
signals.
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Table 8. Intel Pentium

Address Signal Routing Guidelines

Signal Names
Address
Group #1
A[16:3]#
REQ[4:0]#
ADSTB#[0]
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4.1.3.3 Intel Pentium

GMCH (82855GME) FSB Signal Package Lengths

Table 9 lists the preliminary package trace lengths of the Pentium M/Celeron M processor and the
82855GME for the source synchronous data and address signals. The Pentium M/Celeron M
processor FSB package signals within the same group are routed to the same package trace length,
but the Intel 855GME chipset package signals within the same group are not routed to the same
package trace length. As a result of this package length compensation is required for GMCH. Refer
to Section 4.1.4
compensation for further details. The Pentium M/Celeron M processor package traces are routed as
micro-strip lines with a nominal characteristic impedance of 55 Ω ± 15 percent.
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M/Celeron M Processor FSB Design and Power Delivery Guidelines
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M/Celeron M Processor FSB Address Source Synchronous
Signal Strobe Associated with the
Matching
± 200 mils
± 200 mils
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M/Celeron M Processor FSB Source Synchronous
Transmission Line
Type
Address
Group #2
A[31:17]# Strip-line
Strip-line
ADSTB#[1] Strip-line
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M/Celeron M Processor and Intel
for length matching constraints and to
January 2007
6300ESB ICH Embedded Platform Design Guide
Strobe to Associated
Group
ADSTB0#
ADSTB1#
Total Trace Length
Min Max
(inches) (inches)
0.50 6.5
0.50 6.5
0.50 6.5
Section 4.1.4.1
Address Signal Notes
Matching
± 200 mils 1, 2,
± 200 mils 1, 2,
Table 8
Nominal Width and
Impedance Spacing
( Ω )
(mils)
55 ± 15% 4 and 8
55 ± 15% 4 and 8
55 ± 15% 4 and 12
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855GME Chipset
package length
3
3
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