Intel 855GME Design Manual page 304

®
Intel 855GME Chipset and Intel
Layout Checklist
Table 148. Processor Layout Checklist (Sheet 5 of 7)
Checklist Items
TDO
TRST#
TMS
BCLK, BCLK#
304
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
• When ITP700 Is Used :
• Route from CPU pin to a pull-up resistor to
VCCP placed near the debug connector
TDO pin.
• Place a series resistor connecting the pull-up
resistor to the ITP700FLEX debug
connector, limiting trace length from the
series resistor to the debug connector to less
than 1 inch.
• When ITP700 Is Used :
• Route between CPU and debug connector
pin.
• Parallel termination resistor to ground should
be placed anywhere between CPU and
ITP700. Avoid any trace stub from signal line
to parallel termination resistor.
• When ITP700 Is Used :
• Route between CPU and debug connector
pin.
• Parallel termination resistor to VCCP should
be placed within ±200 ps of the ITP700FLEX
debug connector pin.
Other Signals
• Refer to Section 11.2.1 for a detailed
discussion on this topic.
• CPU BCLK, BCLK# from CK409 should be
routed as differential pairs and length
matched to the GMCH BCLK, BCLK#
signals.
• When routing the 100 MHz differential
clocks, do not split up the two halves of a
differential clock pair between layers, and
route to all agents on the same physical
routing layer referenced to ground.
• If a layer transition is required, make sure
that the skew induced by the vias used to
transition between routing layers is
compensated in the traces to other agents.
• Do not place vias between adjacent
complementary clock traces.
• Vias placed in one half of a differential pair
must be matched by a via in the other half.
• Differential vias can be placed within length
L1, between clock driver and Rs, if needed to
shorten length L1.
• When ITP700 Is Used :
• ITP BCLK, BCLK# should be routed with
similar recommendations, but should be
length matched to within ±50 ps of the
system bus clock pairs and the additional
length of the BPM[4:0]# signals, to ensure
correct operation of ITP700FLEX.
Comments
• Refer to host clock group routing
guidelines detailed in
Section 11.2.1.
• Refer to Chapter 10 for detailed
breakdown of all system clock
routing recommendations.