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WITH INTEGRATED FLOATING-POINT UNIT
High-Performance Embedded Architecture
■
— 25 MIPS Burst Execution at 25 MHz
— 9.4 MIPS* Sustained Execution at
25 MHz
On-Chip Floating Point Unit
■
— Supports IEEE 754 Floating Point
Standard
— Full Transcendental Support
— Four 80-Bit Registers
— 13.6 Million Whetstones/s
(Single Precision) at 25 MHz
512-Byte On-Chip Instruction Cache
■
— Direct Mapped
— Parallel Load/Decode for Uncached
Instructions
Multiple Register Sets
■
— Sixteen Global 32-Bit Registers
— Sixteen Local 32-Bit Registers
— Four Local Register Sets Stored
On-Chip (Sixteen 32-Bit Registers per
Set)
— Register Scoreboarding
FOUR
SIXTEEN
80-BIT FP
32-BIT GLOBAL
REGISTERS
REGISTERS
80-BIT
FPU
512-BYTE
INSTRUCTION
INSTRUCTION
FETCH UNIT
CACHE
Figure 1. The 80960MC Processor's Highly Parallel Architecture
© INTEL CORPORATION, 2004
EMBEDDED 32-BIT MICROPROCESSOR
AND MEMORY MANAGEMENT UNIT
64- BY 32-BIT
LOCAL
REGISTER
CACHE
INSTRUCTION
DECODER
80960MC
Commercial
On-Chip Memory Management Unit
■
— 4 Gbyte Virtual Address Space per
Task
— 4 Kbyte Pages with Supervisor/User
Protection
Built-in Interrupt Controller
■
— 32 Priority Levels
— 248 Vectors
— Supports M8259A
— 3.4 µs Latency @ 25 MHz
Easy to Use, High Bandwidth 32-Bit Bus
■
— 66.7 Mbytes/s Burst
— Up to 16 Bytes Transferred per Burst
Multitasking and Multiprocessor Support
■
— Automatic Task dispatching
— Prioritized Task Queues
Advanced Package Technology
■
— 132-Lead Ceramic Pin Grid Array
32-BIT
INSTRUCTION
EXECUTION
UNIT
MICRO-
INSTRUCTION
INSTRUCTION
SEQUENCER
September, 2004
MMU
32-BIT
BUS CONTROL
LOGIC
MICRO-
ROM
Order Number: 273123-002
32-BIT
BURST
BUS
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Table of Contents
Related Manuals for Intel 80960MC
Summary of Contents for Intel 80960MC
- Page 1 EXECUTION CACHE UNIT 80-BIT 32-BIT BUS CONTROL LOGIC MICRO- 512-BYTE MICRO- 32-BIT INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION INSTRUCTION BURST FETCH UNIT DECODER SEQUENCER CACHE Figure 1. The 80960MC Processor’s Highly Parallel Architecture © INTEL CORPORATION, 2004 September, 2004 Order Number: 273123-002...
- Page 2 Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice.
-
Page 3: Table Of Contents
80960MC ® 1.0 THE i960 MC PROCESSOR ........................1 1.1 Key Performance Features ......................... 2 1.1.1 Memory Space And Addressing Modes ................... 4 1.1.2 Data Types ..........................4 1.1.3 Large Register Set ........................4 1.1.4 Multiple Register Sets ......................5 1.1.5 Instruction Cache ........................ - Page 4 Test Load Circuit for Three-State Output Pins ................. 16 Figure 12. Test Load Circuit for Open-Drain Output Pins ................. 16 Figure 13. Drive Levels and Timing Relationships for 80960MC Signals ..........18 Figure 14. Timing Relationship of L-Bus Signals ..................19 Figure 15.
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Page 5: The I960 ® Mc Processor
All members of the i960 processor family share a applications. It includes a 512-byte instruction cache common core architecture which utilizes RISC tech- and a built-in interrupt controller. The 80960MC has nology so that, except for special functions, the a large register set, multiple parallel execution units family members are object-code compatible. -
Page 6: Key Performance Features
Simple Instruction Formats. All instructions in the 80960MC are 32 bits long and must be aligned on word boundaries. This alignment makes it possible to eliminate the instruction alignment stage in the pipeline. -
Page 7: Table 1. 80960Mc Instruction Set
80960MC Table 1. 80960MC Instruction Set Data Movement Process Management Floating Point Logical Load Schedule Process Store Saves Process Subtract Not And Move Resume Process Multiply And Not Load Address Load Process Time Divide Load Physical Address Modify Process Controls... -
Page 8: Memory Space And Addressing Modes
Memory Space And Addressing Modes 1.1.2 Data Types The 80960MC allows each task (process) to address The 80960MC recognizes the following data types: a logical memory space of up to 4 Gbytes. Each task’s address space is divided into four 1 Gbyte... -
Page 9: Multiple Register Sets
When four or more procedures are active and a new processing continues. Since the processor does not procedure is called, the 80960MC moves the oldest need to wait for the LOAD to complete, it can local register set in the stack-frame cache to a... -
Page 10: Memory Management And Protection
1.1.7 Memory Management and Protection 1.1.8 Floating-Point Arithmetic The 80960MC is ideal for multitasking applications In the 80960MC, floating-point arithmetic is an that require software protection and a large address integral part of the architecture. Having the floating- space. To ensure the highest level of performance... -
Page 11: Multitasking Support
1.1.10 Synchronization and Communication passed on the bus and allow multiple processors to run together smoothly, with rare need to lock the bus The 80960MC also offers instructions to set up and or memory. test semaphores to ensure that concurrent tasks remain synchronized and no data inconsistency results. -
Page 12: Interrupt Handling
(usually part of a software debug The 80960MC can be interrupted in two ways: by the monitor). Further program execution is halted until activation of one of four interrupt pins or by sending the routine completes, at which time execution a message on the processor’s data bus. -
Page 13: Inter-Agent Communications (Iac)
DESCRIPTION CLK2 SYSTEM CLOCK provides the fundamental timing for 80960MC systems. It is divided by two inside the 80960MC to generate the internal processor clock. Refer Figure 16, Processor Clock Pulse (CLK2) (pg. 21) LAD31:0 LOCAL ADDRESS / DATA BUS carries 32-bit physical addresses and data to and from memory. - Page 14 80960MC Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 2 of 3) NAME TYPE DESCRIPTION ADDRESS/DATA STATUS indicates an address state. ADS is asserted every T state and deasserted during the following T state. For a burst transaction, ADS is O.D.
-
Page 15: Table 5. 80960Mc Pin Description: Support Signals
80960MC Table 4. 80960MC Pin Description: L-Bus Signals (Sheet 3 of 3) NAME TYPE DESCRIPTION HOLD/ HOLD: A request from an external bus master to acquire the bus. When the HLDAR processor receives HOLD and grants bus control to another master, it floats its three-state bus lines and open-drain control lines, asserts HLDA and enters the T state. - Page 16 80960MC Table 5. 80960MC Pin Description: Support Signals (Sheet 2 of 2) NAME TYPE DESCRIPTION FAILURE INITIALIZATION FAILURE indicates that the processor did not initialize correctly. After RESET deasserts and before the first bus transaction begins, FAILURE O.D. asserts while the processor performs a self-test. When the self-test completes successfully, then FAILURE deasserts.
-
Page 17: Electrical Specifications
= 3.0 V units. Power and ground connections must be made = 20.7 mA to all 80960MC power and ground pins. On the circuit board, all V pins must be strapped closely Figure 4. Connection Recommendations together, preferably on a power plane;... -
Page 18: Figure 6. Typical Supply Current Vs. Case Temperature
80960MC = 5.0 V 25 MHz 20 MHz 16 MHz -60 -40 -20 0 100 120 140 CASE TEMPERATURE (°C) Figure 6. Typical Supply Current vs. Case Temperature TEMP = +22°C @5.5V @5.0V @4.5V OPERATING FREQUENCY (MHz) Figure 7. Typical Current vs. Frequency (Room Temp) -
Page 19: Figure 8. Typical Current Vs. Frequency (Hot Temp)
80960MC TEMP = +22°C @5.5V @5.0V @4.5V OPERATING FREQUENCY (MHz) Figure 8. Typical Current vs. Frequency (Hot Temp) (TEMP = +85°C, V = 4.5V) (TEMP = +85°C, V = 4.5V) FALLING RISING OUTPUT LOW CURRENT(mA) CAPACITIVE LOAD(pF) Figure 9. Worst-Case Voltage vs. Output Current Figure 10. -
Page 20: Test Load Circuit
I legs are not used. When = 50 pF for all signals the 80960MC driver under test is turned off, the output pin is pulled up to V (i.e., V ). Diode D Figure 11. -
Page 21: Dc Characteristics
Power Dissipation ......2.5 W (25 MHz) exposure beyond the “Operating Conditions” may affect device reliability. DC Characteristics PGA: 80960MC (25 MHz) T = 0° C to +85° C, V = 5V ± 5% CASE Table 6. DC Characteristics Symbol... -
Page 22: Ac Specifications
LOCK, INTA 1.5V 1.5V 1.5V VALID OUTPUT 1.5V DT/R INPUTS: LAD31:0 2.0V 2.0V BADAC 0.8V 0.8V IAC/INT0, INT1 INT2/INTR, INT3 VALID INPUT HOLD, HLDAR 2.0V 2.0V LOCK 0.8V 0.8V READY Figure 13. Drive Levels and Timing Relationships for 80960MC Signals... -
Page 23: Figure 14. Timing Relationship Of L-Bus Signals
80960MC CLK2 T 10 T 13 T 11 T 13 Address Data Address Data (31-0) T 8 T 14 ALE# ADS# BE(0:3)# T 13 T 13 T 14 W/R# DT/R DEN# T 11 T 12 T 11 T 12 T 11... -
Page 24: Table 7. 80960Mc Ac Characteristics (25 Mhz)
80960MC Table 7. 80960MC AC Characteristics (25 MHz) Symbol Parameter Units Notes Input Clock Processor Clock Period (CLK2) = 1.5V Processor Clock Low Time (CLK2) = 10% Point = 1.2V Processor Clock High Time (CLK2) = 90% Point = 0.1V + 0.5 V... -
Page 25: Figure 16. Processor Clock Pulse (Clk2)
80960MC HIGH LEVEL (MIN) 0.55V 1.5 V LOW LEVEL (MAX) 0.8V Figure 16. Processor Clock Pulse (CLK2) FIRST CLK2 RESET OUTPUTS INIT PARAMETERS (BADAC, = RESET HOLD /IAC) MUST BE SET UP 8 CLOCKS = RESET SETUP PRIOR TO THIS CLK2 EDGE... -
Page 26: Design Considerations
(e.g., DEN becomes deasserted). The 80960MC is available in one package type: a 132-lead ceramic pin-grid array (PGA). Pins are In other words, whenever the processor generates arranged 0.100 inch (2.54 mm) center-to-center, in a... -
Page 27: Figure 19. 132-Lead Pin-Grid Array (Pga) Package
80960MC A B C D E F G H L M N P Figure 19. 132-Lead Pin-Grid Array (PGA) Package... -
Page 28: Figure 20. 80960Mc Pga Pinout-View From Bottom (Pins Facing Up)
N.C. FAIL N.C. N.C. N.C. N.C. N.C. DT/R LOCK N.C. N.C. N.C. N.C. N.C. N.C. READY CACHE N.C. N.C. N.C. N.C. N.C. HLDA N.C. N.C. HOLD LAD BADAC CLK2 RESET Figure 20. 80960MC PGA Pinout—View from Bottom (Pins Facing Up) -
Page 29: Figure 21. 80960Mc Pga Pinout-View From Top (Pins Facing Down)
FAIL N.C. N.C. N.C. DT/R N.C. N.C. N.C. LOCK N.C. N.C. N.C. READY LAD N.C. N.C. N.C. CACHE LAD N.C. N.C. N.C. N.C. HLDA ADS BADAC HOLD RESET LAD CLK2 Figure 21. 80960MC PGA Pinout—View from Top (Pins Facing Down) -
Page 30: Pinout
80960MC Pinout Table 8. 80960MC PGA Pinout — In Pin Order Signal Signal Signal Signal LOCK N.C. N.C. N.C. N.C. N.C. N.C. /INTA DT/R N.C. N.C. IAC/INT N.C. N.C. N.C. N.C. N.C. HLDA/HOLDR N.C. N.C. /INTR N.C. N.C. FAILURE N.C. -
Page 31: Table 9. 80960Mc Pga Pinout - In Signal Order
80960MC Table 9. 80960MC PGA Pinout — In Signal Order Signal Signal Signal Signal N.C. N.C. N.C. N.C. BADAC N.C. N.C. N.C. N.C. N.C. N.C. N.C. READY N.C. RESET CACHE N.C. CLK2 N.C. N.C. DT/R N.C. FAILURE N.C. HLDA/HOLDR N.C. -
Page 32: Package Thermal Specification
(Omnidirectional J-CAP Heatsink) θ Case-to-Ambient (Unidirectional Heatsink) NOTES: 1. This table applies to 80960MC PGA plugged into socket or soldered directly to board. 2. θ = θ + θ 3. θ = 4°C/W (approx.) J-CAP θ = 4°C/W (inner pins) (approx.) J-PIN θ... -
Page 33: Figure 22. 25 Mhz Maximum Allowable Ambient Temperature
80960MC AIRFLOW (ft/min) PGA with uni- PGA with no PGA with omni- directional heatsink heatsink directional heatsink Figure 22. 25 MHz Maximum Allowable Ambient Temperature... -
Page 34: Waveforms
80960MC WAVEFORMS The following figures present waveforms for various transactions on the 80960MC’S local bus: • Figure 23, Non-Burst Read and Write Transactions Without Wait States (pg. 30) • Figure 24, Burst Read and Write Transaction Without Wait States (pg. 31) •... - Page 35 80960MC CLK2 LAD31:0 BE3:0 DT/R READY Figure 24. Burst Read and Write Transaction Without Wait States...
- Page 36 80960MC CLK2 LAD31:0 BE3:0 DT/R READY Figure 25. Burst Write Transaction with 2, 1, 1, 1 Wait States...
- Page 37 80960MC CLK2 LAD31:0 BE3:2 BE1:0 DT/R READY Figure 26. Accesses Generated by Quad Word Read Bus Request, Misaligned Two Bytes from Quad Word Boundary (1, 0, 0, 0 Wait States)
- Page 38 80960MC PREVIOUS INTERRUPT INTERRUPT IDLE CYCLE ACKNOWLEDGEMENT (5 BUS STATES) ACKNOWLEDGEMENT CYCLE 1 CYCLE 2 CLK2 INTR LAD31:0 ADDR VECTOR ADDR INTA DT/R LOCK READY NOTE: INTR can go low no sooner than the input hold time following the beginning of interrupt acknowledgment cycle 1.
-
Page 39: Revision History
80960MC PBM BUS STATE SBM BUS T hr T hr T hr T hr T hr T hr T hr STATE Addr Data Addr Data Data Addr Addr Data Data Data W/R# PBM ALE# SBM ALE# READY# HOLDR HOLD HLDA...