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®
Intel
855GME Chipset and Intel
4.3
Onboard Debug Port Routing Guidelines
In Intel Pentium M/Celeron M processor-based systems, the debug port should be implemented as
either an onboard debug port or via an interposer. Refer to the ITP700FLEX Debug Port Design
Guide, which may be found on
your platform.
Note: When any differences exist between the general information of the ITP700 Debug Port Design
Guide reference document and this design guide, the implementation recommended in this design
guide takes precedence and should be followed. Specifically, the implementation for the TDO,
RESET#, and BPM[5:0]# signals on the Intel Pentium M/Celeron M processor does differ from the
default ITP debug port recommendations. The changes described below should be adhered to
closely.
4.3.1
Recommended Onboard ITP700FLEX Implementation
4.3.1.1
ITP Signal Routing Guidelines
Figure 36
Intel Pentium M/Celeron M processor, 82855GME, and CK409 clock chip in the cases where the
debug port is used.
For the purpose of this discussion on ITP700FLEX signal routing, refer to
details on the signal propagation time to distance relationships for the length matching
requirements that are listed as periods of time below. It is understood that the time to distance
relationships mentioned in
responsibility of the system designer to determine what is the appropriate length that correlates to
the listed time periods as length matching requirements.
http://developer.intel.com/design/Xeon/guides
illustrates recommended connections between the onboard ITP700FLEX debug port,
Section 4.1.1.4
January 2007
®
6300ESB ICH Embedded Platform Design Guide
apply only to the specific assumptions made and it is the
for the design of
Section 4.1.1.4
for more
77
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