Clk33 Clock Group; Clk33 Group Topology; Clk33 Clock Group Routing Constraints - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
11.2.3

CLK33 Clock Group

The 33 MHz clocks are series terminated and routed point-to point on the motherboard with
dedicated buffers for each of the loads. These clocks are length tuned to match the CLK66 clocks,
however, they are out of phase due to an internal phase delay in the CK409.

CLK33 group topology.

Figure 140. CLK33 Group Topology
CK409
Table 108. CLK33 Clock Group Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Nominal Inner Layer Trace Width
Nominal Outer Layer Trace Width
Minimum Spacing (See exceptions below.)
Serpentine Spacing
Maximum Via Count
Series Termination Resistor Value
Trace Length Limits – L1
Trace Length Limits – L2
Total Length Range – L1 + L2
Length Matching Required
Clock to Clock Matching
Breakout Region Exceptions
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6300ESB ICH Embedded Platform Design Guide
Table 108 presents the CLK33 clock group routing constraints.
L1
Parameter
January 2007
Platform Clock Routing Guidelines
Rs
L2
Definition
CLK33
Individual Nets
Series Terminated Point-to-Point
Ground Referenced
55 Ω ±15%
4.0 mils
5.0 mils (pin escapes only)
20 mils
20 mils
4
33 Ω ±5%
Up to 500 mils
4.0" to 8.5"
CLK66 Length
Yes (Pin to Pin)
±100 mils
CLK33 to CLK33 to CLK66
5 mil trace with 5 mil space on outers
4 mil trace with 4 mil space in inners
Maximum breakout length is 0.3"
Figure 140 depicts the
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Intel 6300ESB
SIO, FWH
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