Package Length Compensation - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Integrated Graphics Display Port
Table 50. DVO Interface Trace Length Mismatch Requirements
Data Group
DVOBD [11:0]
DVOCD [11:0]
NOTES:
1. Data signals of the same group shall be trace length matched to the clock within ± 100 mil including
package lengths.
2. All length matching formulas are based on GMCH die-pad to DVO device pin total length. Package
length tables are provided for all signals to facilitate this pad-to-pin matching.
6.3.2.2

Package Length Compensation

As mentioned in
connector pin. The reason for this is to compensate for the package length variation across each
signal group in order to minimize timing variance. The GMCH does not equalize package lengths
internally as some previous GMCH components have, and therefore, the GMCH requires a length
matching process. Refer to
Table 53
Package length compensation shall not be confused with length matching as discussed in the
previous section. Length matching refers to constraints on the minimum and maximum length
bounds of a signal group based on clock length, whereas package length compensation refers to the
process of adjusting out package length variance across a signal group. There is of course some
overlap in that both affect the target length of an individual signal. Intel recommends that the initial
route be completed based on the length matching formulas in conjunction with nominal package
lengths and that package length compensation be performed as secondary operation.
164
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6300ESB ICH Embedded Platform Design Guide
Signal Matching to
Strobe Clock
±100 mils
±100 mils
Section 6.3.2.1, all length matching is done from GMCH die-pad to DVO
Table 52
for DVOC package lengths information.
DVO Clock Strobes
Associated With the
Group
DVOBCLK[1:0]
DVOCCLK[1:0]
for the DVOB package lengths information and refer to
Clock Strobe Matching Notes
± 10 mils
± 10 mils
1, 2
1, 2