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®
Intel
855GME Chipset and Intel
Schematic Checklist Summary
12.4.6
USB Checklist
Table 137.
USB Checklist
Checklist Items
USBP[0:3]P,
USBP[0:3]N
OC[0:3]#
USBRBIAS#
USBRBIAS
CLK48
12.4.7
Power Management Checklist
Table 138.
Power Management Checklist (Sheet 1 of 2)
Checklist Items
PWROK
RSMRST#
PWRBTN#
RI#
SLP_S3#,
SLP_S4#,
SLP_S5#
SUS_STAT#/LPCPD#
SUSCLK
290
®
6300ESB ICH Embedded Platform Design Guide
Recommendations
No external resistors are required.
No external resistors are required.
Connected to the same 22.6 Ω ±1%
resistor to GND as USBRBIAS.
22.6 Ω ±1% connected to GND.
Ensure this pin is connected to a
48MHz clock output of the clock
generator (CK409) through a 33 Ω
resistor
Recommendations
Recommend a 10 K Ω pull-down to GND.
This signal should be connected to
power monitoring logic, and should go
high no sooner than 100 ms after both
V
3.3 and V
1_5 have reached their
CC
CC
nominal voltages.
Recommend a 10 K Ω pull-down resistor
to GND.
This signal should be connected to
power monitoring logic, and should go
high no sooner than 10 ms after both
V
Sus3.3 and V
Sus1_5 have
CC
CC
reached their nominal voltages.
No extra pull-up resistors
RI# does not have an internal pull-up.
Recommend an 8.2 K Ω pull-up resistor
to V
Sus3.3
CC
No pull up/down resistors needed.
No extra pull-up resistors
No extra pull-up resistors
Interface Not Used
Effective output driver
May leave as no
impedance of 45 Ω
connect
provided.
May leave as no
connect
May leave as no
connect
May leave as no
connect
May leave as no
connect
Reason/Impact
Timing Requirement
Timing Requirement
This signal has an integrated pull-up of
18 K Ω - 42 K Ω . This signal is internally
debounced inside the 6300ESB.
When this signal is enabled as a wake
event, it is important to keep this signal
powered during the power loss event. If
this signal goes low (active), when power
returns the RI_STS bit will be set and the
system will interpret that as a wake event.
Signals driven by 6300ESB
Driven by the 6300ESB
Driven by the 6300ESB
Reason/Impact
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