Host Clock Group Routing Constraints - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
Platform Clock Routing Guidelines
Table 105. Host Clock Group Routing Constraints
Class Name
Class Type
Topology
Reference Plane
Single Ended Trace Impedance (Zo)
Differential Mode Impedance (Zdiff)
Nominal Inner Layer Trace Width
Nominal Inner Layer Pair Spacing (edge to edge)
(except as allowed below)
Nominal Outer Layer Trace Width
Nominal Outer Layer Pair Spacing (edge to edge)
(except as allowed below)
Minimum Spacing to Other Signals
Serpentine Spacing
Maximum Via Count
Series Termination Resistor Value
Shunt Termination Resistor Value
Trace Length Limits – L1 & L1'
Trace Length Limits – L2 & L2'
Trace Length Limits – L3 & L3'
Trace Length Limits – L4 & L4'
Total Length Range– L1 + L2 + L4
Length Matching Required
HCLK to HCLK# Length Matching
CPU Clock to GMCH Clock Length Matching
Breakout Region Exceptions
NOTES:
1. Differential pairs should be routed as a closely coupled side-by-side pair on a single layer over their entire
length.
2. To minimize skew it is recommended that all clocks be routed on a single layer. If clock pairs are to be
routed on multiple layers, the routed length on each layer should be equalized across all clock pairs.
3. To minimize skew it is recommended that all clock pairs be length matched from CK409 pin to CPU and
GMCH die-pad, and length compensated on the motherboard for differences in package length and for
socket/interposer effective length. A table of package lengths and equivalent socket length is provided.
4. The motherboard length of the ITP connector clock pair should be matched to the motherboard length of
the CPU clock pair plus the length of the BPM#[4:0] signals, within ± 50 ps.
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6300ESB ICH Embedded Platform Design Guide
Parameter Definition
HOST_CLK
Individual Differential Pairs
Differential Source Shunt Terminated
Ground Referenced (contiguous over length)
55 Ω ±15%
100 Ω ±15%
4.0 mils
7.0 mils
5.0 mils (pin escapes only)
5.0 mils
25 mils
25 mils
5 (per side)
33 Ω ±5%
49.9 Ω ±1%
Up to 500 mils
Up to 200 mils
Up to 500 mils
2.0" to 8.0"
2.0" to 8.5"
Yes (Pin to Pad)
± 10 mils (per segment)
± 10 mils (overall)
Match HCLKs (pin to pad) ± 20 mils
Match L1 segment to ± 10 mils across all pairs.
Refer to Section 11.2.1.2 for more information.
No breakout exceptions allowed.