Intel ® 855Gme Chipset Gmch (82855Gme) Layout Checklist - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
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13.2 Intel
Layout Checklist
Table 149
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Table 149. Intel 855GME Chipset GMCH Layout Checklist (Sheet 1 of 6)
Checklist Items
ADS#
BNR#
BPRI#
1
BREQ0#
CPURST#
DBSY#
DEFER#
HA[31:3]#
HD[63:0]#
HADSTB[1:0]#
HDSTBN[3:0]#
HDSTBP[3:0]#
HIT#
HITM#
10
HLOCK#
HREQ[4:0]#
9
HTRDY#
DRDY#
RS[2:0]#
DINV[3:0]#
SCK[5:0]
SCK[5:0]#
855GME Chipset GMCH (82855GME)
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presents the Intel 855GME chipset GMCH layout checklist.
Recommendations
2
3
4
5
• Refer to the Processor section of this
6
checklist.
7
8
DDR System Memory Interface
• Refer to the detailed discussion on this
topic in Section 5.4.3
• Route as closely-coupled differential pairs,
3 clock pairs to each DIMM.
• Spacing to other DDR signals should not
be less than 20 mils. Isolation from non-
DDR signals should be 25 mils.
• Route on internal layers, except for pin
escapes.
• Nominal internal trace width 7 mils and
nominal internal spacing 4 mils.
• Routed trace length limits are 3.5 to 6.5
inches.
• Length match clock pairs to ±10 mils.
• Match all DIMM0 clocks to X0 ± 25 mils
• Match all DIMM1 clocks to X1 ± 25 mils
• Match all DIMM0 clock lengths and match
all DIMM1 clock lengths.
• Use GMCH package lengths for pad-to-
pin length tuning.
• Differential mode impedance is
70 ohms ± 15%
• Maximum breakout length is 0.3 inches
• Maximum via count of 2 per side
January 2007
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6300ESB ICH Embedded Platform Design Guide
Host Interface Signals
• Refer to the detailed routing
Layout Checklist
Comments
guidelines in Section 5.4.3.
307