Intel 855GME Design Manual page 9

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Intel 855GME Chipset and Intel
9.10.1 66 MHz Topologies and Trace Length................................................................. 229
9.10.1.1 PCI-X Clock Length Matching Guidelines ............................................ 231
9.10.2 IDSEL Series Resistor ......................................................................................... 231
9.10.3 PCI-X Secondary Bus Reset ............................................................................... 232
9.10.3.1 Secondary Bus Reset Not Utilized ....................................................... 232
9.10.4 PME# Signal Sharing........................................................................................... 232
9.10.4.1 Issues with Sharing PME# ................................................................... 232
9.11 RTC .................................................................................................................................. 233
9.11.1 RTC Crystal ......................................................................................................... 234
9.11.2 External Capacitors ............................................................................................. 235
9.11.3 RTC Layout Considerations................................................................................. 236
9.11.4 RTC External Battery Connection........................................................................ 236
9.11.5 RTC External RTCRST# Circuit........................................................................... 238
9.11.6 VBIAS DC Voltage and Noise Measurements ..................................................... 238
9.11.7 SUSCLK .............................................................................................................. 239
9.11.8 RTC-Well Input Strap Requirements ................................................................... 239
9.12 Serial I/O ........................................................................................................................... 239
9.12.1 Serial I/O Interface Not Utilized ........................................................................... 239
9.13 FWH.................................................................................................................................. 240
9.13.1 FWH Vendors ......................................................................................................240
9.13.2 FWH Decoupling.................................................................................................. 240
9.13.3 In-circuit FWH Programming................................................................................ 240
9.13.4 FWH INIT# Voltage Compatibility ........................................................................ 240
9.13.5 FWH VPP Design Guidelines .............................................................................. 241
9.14 GPIO Summary ................................................................................................................ 242
9.15 Power Management.......................................................................................................... 244
9.15.1 SYS_RESET# Usage Model ............................................................................... 244
9.15.2 PWRBTN# Usage Model ..................................................................................... 244
9.15.3 Power-Well Isolation Control Strap Requirements............................................... 244
10 Miscellaneous Logic ................................................................................................................. 247
10.1 Glue Chip 4* ..................................................................................................................... 247
10.2 Discrete Logic ................................................................................................................... 248
11 Platform Clock Routing Guidelines ......................................................................................... 249
11.1 System Clock Groups ....................................................................................................... 249
11.2 Clock Group Topologies and Routing Constraints............................................................ 251
11.2.1 Host Clock Group ................................................................................................ 251
11.2.1.1 Host Clock Group General Routing Guidelines ................................... 253
11.2.1.2 Clock-to-Clock Length Matching and Compensation ........................... 253
11.2.1.3 EMI Constraints ...................................................................................253
11.2.2 CLK66 Clock Group ............................................................................................. 254
11.2.3 CLK33 Clock Group ............................................................................................. 255
11.2.4 PCI Clock Group .................................................................................................. 256
11.2.5 CLK14 Clock Group ............................................................................................. 257
11.2.6 DOTCLK Clock Group ......................................................................................... 258
11.2.7 SSCCLK Clock Group ......................................................................................... 259
11.2.8 USBCLK Clock Group ......................................................................................... 260
11.2.9 SRC Clock Group ................................................................................................ 261
11.2.9.1 SRC Clock Topology............................................................................261
11.2.9.2 SRC General Routing Guidelines ........................................................ 263
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6300ESB ICH Embedded Platform Design Guide
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