Mechanical Considerations; Electrical Considerations; Processor Phase Lock Loop (Pll) Design Guidelines; Processor Pll Power Delivery - Intel 855GME Design Manual

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Intel 855GME Chipset and Intel
4.3.3.1

Mechanical Considerations

The LAI is installed between the processor socket and the Intel Pentium M/Celeron M processor.
The LAI pins plug into the socket, while the Intel Pentium M/Celeron M processor in the 478-pin
package plugs into a socket on the LAI. Cabling this part of the LAI egresses the system to allow
an electrical connection between the Intel Pentium M/Celeron M processor and a logic analyzer.
The maximum volume occupied by the LAI, known as the keepout volume, as well as the cable
egress restrictions, should be obtained from the logic analyzer vendor. System designers must
make sure that the keepout volume remains unobstructed inside the system.
Note: It is possible that the keepout volume reserved for the LAI may include space normally occupied
by the Intel Pentium M/Celeron M processor heat sink. When this is the case, the logic analyzer
vendor shall provide a cooling solution as part of the LAI.
4.3.3.2

Electrical Considerations

The LAI also affects the electrical performance of the Intel Pentium M/Celeron M processor
system bus. Therefore, it is critical to obtain electrical load models from each of the logic analyzers
to be able to run system level simulations to prove that their tool works in the system. Contact the
logic analyzer vendor for electrical specifications as load models for the LAI solution they provide.
4.3.4

Processor Phase Lock Loop (PLL) Design Guidelines

4.3.4.1

Processor PLL Power Delivery

V [3:0] is a power source required by the PLL clock generators on the processor silicon.
CCA
Because these PLLs are analog in nature, they require quiet power supplies for minimum jitter.
Jitter is detrimental to the system because it degrades external I/O timings as well as internal core
timings (i.e., maximum frequency). Traditionally this supply is low-pass filtered to prevent any
performance degradation. The Intel Pentium M/Celeron M processor has an internal PLL super
filter for the 1.8 V supply to the VCCA [3:0] pins that dispenses with the need for any external
low-pass filtering. However, one 0603 form factor 10 nF and one 1206 form factor 10 µF
decoupling capacitor should be placed as close as possible to each of the four VCCA pins (i.e., a
pair of capacitors consisting of one 10 nF and one 10 µF should be used for each VCCA pin).
VCCA power delivery should meet the 1.8 V ± 5 percent tolerance at the VCCA pins. As a result,
to meet the current demand of the Intel Pentium M/Celeron M processor and the future Intel
Pentium M/Celeron M processor family, it is strongly recommended that the VCCA feed resistance
from the 1.8 V power supply up to the VCCA shorting scheme described below be less than 0.1 Ω .
It is recommended that the main VCCA feed be connected to the Intel Pentium M/Celeron M
processor VCCA1 pin. Refer to
decoupling requirements.
Figure 40
decoupling. The 1.8 V flood on Layer 3 from the Intel 855GME chipset is a via routed up to the
primary side layer with a cluster of five 1.8 V vias and two GND stitching vias as shown on the left
and middle side of
VCCA[3:0] pins of the processor. To minimize resistance and inductance of the U-shaped VCCA
flood shorting the VCCA[3:0] pins, the flood should be at least 100 mils wide and be spaced at
least 25 mils from any switching signals. When possible, a flood wider than the 100 mil minimum
shall be implemented and shall reference a ground plane only. Do not reference any switching
signals or split planes. The recommended wide flood on the primary side benefits from low
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6300ESB ICH Embedded Platform Design Guide
Section 4.3.4.3
illustrates the recommended layout example of the VCCA[3:0] pins feed and
Figure 40. On the primary layer side, a wide flood in a U-shape shorts the four
for Intel Pentium M/Celeron M processor PLL