Voltage Translation Logic - Intel 855GME Design Manual

®
Intel 855GME Chipset and Intel
Figure 21. Routing Illustration for Topology 3
Table 16. Layout Recommendations for Topology 3
L1 + L2
0.5" – 12.0"
0.5" – 12.0"
4.1.5.7

Voltage Translation Logic

A voltage translation circuit or component is required on any signals where the voltage signaling
level between two components connected by a transmission line may cause unpredictable signal
quality. The recommended voltage translation circuit for the platform is shown in
the INIT# signal
where the driver isolation resistor, Rs, is place at the beginning of a transmission line that connects
to the first bipolar junction transistor, Q1. Though the circuit shown in
work with signals that require translation from a 1.05 V to a 3.3 V voltage level, the same topology
and component values, in general, may be adapted for use with other signals as well, provided the
interface voltage of the receiver is also 3.3 V. Any component value changes or component
placement requirements for other signals must be simulated in order to ensure good signal quality
and acceptable performance from the circuit.
In addition to providing voltage translation between driver and receiver devices, the recommended
circuit also provides filtering for noise and electrical glitches. A larger first-stage collector resistor,
R1, may be used on the collector of Q1, however, it results in a slower response time to the output
falling edge. In the case of the INIT# signal, resistors with values as close as possible to those listed
in Figure 22
With the low 1.05 V signaling level of the Intel Pentium M/Celeron M processor system bus, the
voltage translation circuit provides ample isolation of any transients or signal reflections at the
input of transistor Q1 from reaching the output of transistor Q2. Based on simulation results, the
voltage translation circuit may effectively isolate transients as large as 200 mV and that last as long
as 60 ns.
®
Intel
6300ESB
CPU
I/O
Controller
L2 L1
Rs
L3 L4
0" – 3.0" 0.5" – 6.0"
0" – 3.0" 0.5" – 6.0"
(Section 4.1.5.6), a specialized version of this voltage translator circuit is used
shall be used without exception.
January 2007
®
6300ESB ICH Embedded Platform Design Guide
3.3V
R1
Q2
Q1
L3
3904
Rs R1
330 Ω ± 5% 1.3 k Ω ± 5%
330 Ω ± 5% 1.3 k Ω ± 5%
FWH
3.3V
V_IO_FWH
R2
L4
3904
B3161-01
Transmission
R2
Line Type
330 Ω ± 5%
Micro-strip
330 Ω ± 5%
Strip-line
Figure 22. For
Figure 22 was developed to
63